10:29 <key2> hey

10:29 <key2> just out of curiosity, has anyone looked at amber cpu and eventually how hard it would be to add it to misoc, as well as if it has an advantage toward lm32 for example ?

10:42 <whitequark> ARMv2?

10:48 <sb0> this? http://opencores.org/project,amber

10:48 <sb0> forget it.

10:49 <sb0> no advantage, only bugs, slowness, bloat etc.

10:50 <sb0> if you want a fashionable cpu, riscv recently boasted about a lattice implementation that may be good, if it's not vaporware

10:56 <key2> aha

10:59 <key2> sb0: a while ago, I thought about porting nuttx for lm32 or mor1kx but then lost interest. But still believe it could be fancy to have nuttx runnin on lm32.

12:51 <cr1901> sb0: Lattice implementation? Meaning RISC-V and lm32 are so similar to the extent that instructions in one can be converted to the other?

12:53 <key2> what is the url of the risc-v cpu ?

12:54 <key2> is it this one ? http://riscv.wpengine.com/

17:53 <key2> sb0: in here https://github.com/m-labs/drtio_transceiver_test/blob/master/wbtest.py , at what address do you read back the deadbeef ?