00:15 <rjo> the things described in the readme work. yes.

02:27 <sb0> rjo, do all ultrascale devices use SSI?

02:28 <sb0> afaict ultrascale is a fancy marketing term for 7-series with a finer process, a couple additions like larger block rams ("ultraram" for the marketing guys) and a few minor architecture changes

03:22 <sb0> whitequark, please do not disturb the kc705s for the next couple hrs

03:24 <whitequark> okay

05:42 <sb0> whitequark, you can use the kc705s

05:43 <sb0> for the hardware tests, have a look at the wishbonebridge and comm_uart modules from drtio_transceiver_test

05:43 <sb0> they should help you with debugging

05:44 <sb0> and it is a good idea to leave those modules in the final design, so we can use them to e.g. tweak the phase of the si5324 output

08:12 <GitHub104> [migen] whitequark pushed 1 new commit to master: https://git.io/vKjlF

08:12 <GitHub104> migen/master d535f90 whitequark: Fix NextState(signal[x:y], ...).

08:13 <bb-m-labs> build #82 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/82

08:16 <bb-m-labs> build #116 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/116

08:34 <bb-m-labs> build #571 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/571

08:39 <bb-m-labs> build #284 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/284

08:44 <bb-m-labs> build #846 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/846

09:24 <rjo> sb0: no. only the fatter ones use ssi. that ku040 not yet, but iirc ku085 or ku090 or the like. they have a table in the family datasheet.

09:25 <rjo> sb0: i would agree with your description of ultrascale. ultrascale+ is even more obscure.

09:45 <rjo> sb0: ku085 has two SLRs (super-logic regions, i read it simply as: dies)

11:05 <whitequark> sb0: hm. can't figure out why ise optimizes out the entire design.

11:05 <GitHub74> [si5324_test] whitequark pushed 1 new commit to master: https://github.com/m-labs/si5324_test/commit/d6900c4b3f6c9ec89c4d3455900efd390cb08d24

11:05 <GitHub74> si5324_test/master d6900c4 whitequark: Add FSM-based I2C core and core sequencer (WIP).

11:06 <GitHub157> si5324_test/master 9b52d68 whitequark: Add FSM-based I2C core and core sequencer (WIP).

11:06 <GitHub157> [si5324_test] whitequark force-pushed master from d6900c4 to 9b52d68: https://github.com/m-labs/si5324_test/commits/master

11:06 <whitequark> oh it stopped doing that for some reason. weird.

11:32 <sb0> whitequark, was the memory empty?

11:33 <sb0> xilinx tools do look at the content of memories, and optimize what is connected to it accordingly

11:38 <rjo> nice how migen tells you gently through naming things that your design is getting pretty big: top_channel7_dds7_cordic63_z16_reg ...

11:48 <whitequark> ise is ridiculously slow

11:48 <rjo> whitequark: i am competing for cpu and ram with you right now.

11:48 <rjo> will be done soon hopefully

11:48 <whitequark> this design has two hundred LUTs, it still takes 30s on a good day

11:50 <rjo> yes. even building a 1 or 2 LUT design (the jtag proxy bitstream) for all xilinx chips, takes a good hour.

11:53 <whitequark> that's ridiculous.

11:56 <whitequark> sb0: ok. it works as i want on pipistrello.

11:57 <whitequark> tomorrow i'll go to the lab and verify that it does the same for kc705.

11:57 <GitHub42> [si5324_test] whitequark pushed 1 new commit to master: https://github.com/m-labs/si5324_test/commit/bc1d9d6a87ab80fd0d1a849428653116735a9775

11:57 <GitHub42> si5324_test/master bc1d9d6 whitequark: Working FSM-based I2C core, wrapped for Pipistrello as a test.

11:59 <whitequark> btw, what's the best way to observe i2c communication on kc705? none of the ports on it are especially convenient

11:59 <whitequark> oh, i guess i could put it on the hpc connector and use the socket on the backplane.

12:02 <rjo> whitequark: or that xadc/ams101 thing which has a few pin headers.

12:03 <whitequark> right, that works too.

12:22 <rjo> sb0: by the way: interestingly, there seem to be no 10g sfp+ bidi transcievers for 1310/1490. they all do that at 1270/1330, which should actually be much better for WR and us, from a fiber-physics perspective.

12:23 <rjo> and it is impressive that they get sharp dichroics.

12:43 <sb0> rjo, ok. 10g sounds good.

13:07 <sb0> whitequark, okay, can you make it work with the si5324 chip, 62.5MHz in and out

13:07 <sb0> and please update the sequencer unittest since you modified it

15:49 <sb0> https://github.com/m-labs/si5324_test/blob/master/i2c.py#L199 << so writing to config can cause transfers?

15:49 <sb0> whitequark, ^

15:50 <sb0> I would not implement registers with an Array like that, but simply case/if on addr

15:50 <sb0> they're not really a memory, they have dynamic behavior

15:50 <sb0> and get rid of that combinatorial feedback. https://github.com/m-labs/si5324_test/blob/master/i2c.py#L188

16:22 <GitHub114> [artiq] jordens deleted phaser at d928455: https://git.io/vKjiU

22:42 <whitequark> sb0: hm, right, Array is a bad choice

22:47 <whitequark> but getting rid of Record makes for very ugly code