sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> altker128, not in any active project, but it worked fine for usb on the milkymist
<sb0> altker128, what are you doing?
<altker128> sb0: Just exploring uCs in FPGAs
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<altker128> Mico8 looks interesting because there's a C compiler for it too
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<sb0> is mico8 free?
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<altker128> sb0: Yes, just like mico32, they both came from Lattice
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<sb0> but mico8 had a different license
<altker128> Claims to be open
<altker128> Well, there's no debugger support for mico8 . So, that's sucks. It does have a C-compiler though
<sb0> why do you need a debugger that much?
<altker128> In my experience they're invaluable.
<altker128> You don't need it all the time, but when you need it, you really need it.
<altker128> There's an openMSP430 core that has debug support but its logic / resource usage is pretty high
<sb0> most open source cores are slow, buggy and bloated, yes
<altker128> I think in this case an FPGA implementation of MSP430 will just be big due to the complexity of the architecture
<altker128> Same with most softcore processors
<sb0> wrong
<altker128> Let me re-phrase. Most softcore processors which emulate an existing ISA
<sb0> the usual reasons are sloppiness, laziness and incompetence
<altker128> OK.
<altker128> Have you come across any softcore processors that are well designed and low in resources?
<sb0> yes, lm32 and mor1kx
<sb0> lm32 has cleaner isa
<sb0> they have debuggers too, it's just that no one has bothered to expose them in misoc
<altker128> Have you personally tried the debugging?
<sb0> not really
<sb0> just the lm32 one a bit, over serial gdb
<altker128> What was your experience?
<sb0> works alright afaict. but i don't use debuggers.
<altker128> Good to know! Serial debugging (with a sufficiently high baudrate) is very reasonable
<sb0> milkymist soc has support for it, and it should be straightforward to port to misoc
<GitHub87> [artiq] sbourdeauducq pushed 1 new commit to release-1: https://git.io/vKluC
<GitHub87> artiq/release-1 972a742 Sebastien Bourdeauducq: monkey-patch Python 3.5.2 to disable broken asyncio.base_events._ipaddr_info optimization (#506)
<sb0> bb-m-labs, force build --branch=release-1 artiq
<bb-m-labs> build forced [ETA 20m20s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> bb-m-labs, stop build artiq xxxx
<bb-m-labs> build 811 interrupted
<bb-m-labs> build #811 of artiq is complete: Exception [exception interrupted] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/811
<GitHub5> [artiq] sbourdeauducq pushed 1 new commit to release-1: https://git.io/vKluz
<GitHub5> artiq/release-1 c27f157 Sebastien Bourdeauducq: make sure monkey patches are applied when asyncio.open_connection() is used
<sb0> bb-m-labs, force build --branch=release-1 artiq
<bb-m-labs> build forced [ETA 20m20s]
<bb-m-labs> I'll give a shout when the build finishes
<GitHub105> [artiq] sbourdeauducq pushed 1 new commit to master: https://git.io/vKlzI
<GitHub105> artiq/master 1c32d4f Sebastien Bourdeauducq: monkey-patch Python 3.5.2 to disable broken asyncio.base_events._ipaddr_info optimization (#506)
<sb0> bb-m-labs, force build --branch=release-1 artiq-pipistrello-nist_qc1
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<sb0> bb-m-labs, force build --branch=release-1 artiq-kc705-nist_qc2
<sb0> bb-m-labs, force build --branch=release-1 artiq-kc705-nist_qc1
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> build #537 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/537
<bb-m-labs> build forced [ETA 27m34s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> rjo, seems your spi change broke timing on pipistrello, in addition to tickling vivado bugs on kc705
<sb0> do we need spi on pipistrello?
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<bb-m-labs> build #231 of artiq-pipistrello-nist_qc1 is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-pipistrello-nist_qc1/builds/231
<bb-m-labs> build forced [ETA 23m43s]
<bb-m-labs> I'll give a shout when the build finishes
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<bb-m-labs> build #174 of artiq-kc705-nist_qc2 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_qc2/builds/174
<bb-m-labs> build #182 forced
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #257 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/257
<bb-m-labs> build #812 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/812
<bb-m-labs> build #182 of artiq-kc705-nist_qc1 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_qc1/builds/182
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<rjo> sb0: seems hasty.
<rjo> sb0: the master builds work fine.
<bb-m-labs> build #538 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/538
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<rjo> sb0: could be your change just as well.
<sb0> bb-m-labs, force build artiq-pipistrello-nist_qc1
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<sb0> what change?
<sb0> the reset clock domain?
<rjo> sb0: i already have two builds queued.
<rjo> sb0: yes
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<sb0> "12. Shall have FPGA logic cells of 325,000 or greater" (NIST solicitation)
<sb0> I wonder how they define "logic cell" ....
<cr1901_modern> Maybe the classic 4-LUT + flip-flop?
<sb0> modern FPGAs don't have 4-LUTs
<sb0> and that would be a huge FPGA for what the rest of the solicitation asks for
<cr1901_modern> Lattice ICE40 has 4-LUTs... so maybe they don't know exactly what size FPGA they're asking for :P? Logic gates maybe?
<sb0> can the ice40 do better than arduino-level stuff?
<whitequark> have you seen arduinos running at 150MHz?
<cr1901_modern> sb0: It has LVDS transceivers, so it can do HDMI under its own power. Not very high res HDMI, but something!
<altker128> sb0: Have you seen this? : http://lxp32.github.io/
<whitequark> well, I guess you actually have, with the cortex-m ones
<whitequark> in that case the answer is no, not really, it cannot
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<cr1901_modern> I doubt a random microcontroller can spit out pixel data fast enough for HDMI with the correct timing requirements. But I'm sure someone has done it...
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<GitHub69> [artiq] whitequark pushed 1 new commit to master: https://git.io/vKlHV
<GitHub69> artiq/master c50d436 whitequark: ir: `invoke` is a valid `delay` decomposition....
<bb-m-labs> build #232 of artiq-pipistrello-nist_qc1 is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-pipistrello-nist_qc1/builds/232
<bb-m-labs> build #813 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/813 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build forced [ETA 27m34s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #233 of artiq-pipistrello-nist_qc1 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-pipistrello-nist_qc1/builds/233
<bb-m-labs> build #234 of artiq-pipistrello-nist_qc1 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-pipistrello-nist_qc1/builds/234
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<bb-m-labs> build #539 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/539
<bb-m-labs> build #258 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/258 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #814 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/814 blamelist: whitequark <whitequark@whitequark.org>
<GitHub37> [llvm-or1k] whitequark force-pushed artiq from 4e3f942 to e26c4d6: https://github.com/m-labs/llvm-or1k/commits/artiq
<GitHub37> llvm-or1k/artiq 1f6ef11 whitequark: [OR1K] Override TargetLowering::useSoftFloat().
<GitHub37> llvm-or1k/artiq 86b70e9 whitequark: [OR1K] Cleanup formatting (NFC).
<GitHub37> llvm-or1k/artiq 22c3ccb whitequark: [OR1K] Model flag, overflow flag and carry flag separately.
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<key2> Hi
<key2> if I do this " self.sync += [x.eq(1), x.eq(0)]" in a module, x would be equal to what at each sys_clk ?
<cr1901_modern> x would always equal 0 I believe
<cr1901_modern> Your Migen code will generate something similar
<key2> I believe
<key2> but what i am interested is the behavour in the fpga, and if it is deterministic
<key2> what is the difference between "self.sync += [x.eq(1), x.eq(0)]" and "self.sync += [x.eq(0), x.eq(1)]"
<rjo> an fpga doesn't work like that. the assignments get flattened way before it hits the fpga.
<key2> yes but into what
<key2> into a 0 or a 1 ?
<rjo> as cr1901_modern said
<rjo> except the first cycle
<cr1901_modern> It's "except the first cycle" because FPGAs have hardware provisions to set a power-on value for wires and registers (I'm not sure how it's implemented)
<larsc> both assignments execute at the same time, but in the order specified, if that makes any sense
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<key2> larsc: if I had flipflops or registers, I would say that it makes no sens to put on the same input pin a 1 and a 0 without any logic gate in front
<larsc> key2: yeah, this is just a construct that exists in the HDL language, the synthesizer will transform this into something that will only have a single driver.
<key2> but for example, here:
<larsc> the reason why you can assign a register multiple times in the same block is so you can do stuff like this: 'x <= 1; if (y) x <= 0;'
<larsc> yep, exactly the same as my example
<key2> yes
<key2> so what is the rule here ?
<larsc> the synthezier will turn this into if (y) x <= 0; else x <= 1
<larsc> it's just semantic sugar
<key2> I see
<larsc> so you don't have to provide a else statement on each path
<key2> so basically, this way, it helps not havint to define the else at the proper place which makes a lot of if/else inside eachother ?
<key2> Ok
<larsc> yes
<key2> I could define the general behavour on a always@ block
<key2> and
<key2> have the case somewhere else
<key2> and the synth would do the job
<key2> but in this case for example
<key2> would the simulation do the same as what the synth would do ?
<larsc> yes
<key2> ok
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<key2> when simulating a module, how do you trigger a sys_rst ?
<key2> dut.sys_rst.eq(1) seams to be incorrect
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<key2> is there a way to reduce with "add" for a signal ?
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<GitHub70> [artiq] jordens pushed 1 new commit to master: https://git.io/vK8Az
<GitHub70> artiq/master c0d5914 Robert Jordens: pc_rpc: increase firstcon_timeout to 1 s...
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<GitHub110> [artiq] sbourdeauducq pushed 1 new commit to release-1: https://git.io/vK8j6
<GitHub110> artiq/release-1 1d58e3c whitequark: ir: `invoke` is a valid `delay` decomposition....
<bb-m-labs> build #540 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/540
<bb-m-labs> build #259 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/259 blamelist: Robert Jordens <rj@m-labs.hk>
<bb-m-labs> build #815 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/815 blamelist: Robert Jordens <rj@m-labs.hk>
<sb0> bb-m-labs, force build --revision=eceafad7e30ac4c0cfd47db08c9f086ede5f6dba artiq-pipistrello-nist_qc1
<bb-m-labs> build forced [ETA 35m40s]
<bb-m-labs> I'll give a shout when the build finishes
<whitequark> rjo: that test is really fragile.
<whitequark> we're running it with exclusive access to the buildserver and it fails all the time
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<bb-m-labs> build #235 of artiq-pipistrello-nist_qc1 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-pipistrello-nist_qc1/builds/235
<sb0> bb-m-labs, force build --revision=078a9abeb95e32de949d225b7f9680b817992ba0 artiq-pipistrello-nist_qc1
<bb-m-labs> build forced [ETA 30m55s]
<bb-m-labs> I'll give a shout when the build finishes
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<bb-m-labs> build #236 of artiq-pipistrello-nist_qc1 is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-pipistrello-nist_qc1/builds/236
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