#m-labs on 2015-01-28 — irc logs at freenode.irclog.whitequark.org

2013-12-11 12:34 lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs

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08:28 <GitHub151> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/FBqc

08:28 <GitHub151> artiq/master 906099c Sebastien Bourdeauducq: gui/rt_results: do not attempt to plot before receiving data

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10:09 <larsc> hm, so when should a composite actor be busy?

10:33 <sb0> when at least one of its sub-actors is

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10:35 <larsc> yea, for some reason the sub-actors are idle, but the dma composite actor is still busy

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13:05 <larsc> yep, something is seriously broken with this transmitter http://postimg.org/image/9lydah65b/

13:05 <larsc> red is vsync

13:05 <larsc> good image for reference

13:05 <larsc> http://postimg.org/image/d2tb0sx5f/

13:37 <sb0> testing ADI chips?

13:42 <larsc> yea, but it's bridge chip, the timing is generated by a SoC

13:42 <larsc> I think it's a problem of garbage in, garbage out

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14:15 <larsc> or does HDMI actually have support for vsync active low?

14:15 <larsc> that would explain the inverted vsync

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14:22 <sb0> there is support for it in DVI, and as a general rule the computer industry doesn't fail to carry forward a stupid idea

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14:25 <larsc> yea

14:25 <larsc> but still the total line length jitters

14:25 <larsc> by one pixel every few lines

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20:02 <GitHub25> [artiq] jboulder closed pull request #8: Controller for 4 channel DDS used in several ion storage labs. (master...master) http://git.io/2xqKqA

20:02 <GitHub32> [artiq] jboulder reopened pull request #8: Controller for 4 channel DDS used in several ion storage labs. (master...master) http://git.io/2xqKqA

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