<corecode_>
sb0: i was trying to find information how to port misoc to lattice xo2, especially the LPDDR part
<sb0>
well you have to write a new phy, essentially
<sb0>
and add support for the lattice tools to mibuild
<corecode_>
right
<corecode_>
i was looking for testbenches for the existing phys/controllers to bootstrap from, but i couldn't find them
<corecode_>
am i looking wrong?
<sb0>
_florent_ might have some testbenches, but they require modelsim and some imbecilic xilinx encrypted "IP"
<sb0>
anyway all that the PHY do is serialize/deserialize the SDRAM IOs and sort out timing
<sb0>
you need to study closely how the SERDES works on that FPGA and how you can use that to talk to LPDDR
<corecode_>
to be honest, i'm having trouble penetrating the python syntax
<ysionneau>
I have some code somewhere with testbench for simplesdramcon for DDR and SDRAM phy, but the testbenches are not working perfectly unfortunately (for the phy part), it's using the models of ODDR2 and stuff from Xilinx, and running under iverilog
<ysionneau>
maybe I could share and you could be able to fix it
<corecode_>
maybe that's because i am new at hardware design
<sb0>
the main issue won't be the python syntax I think. more understanding how SERDES, PLLs, IO timings and DRAM work - it'll take you a while. when I was new to hardware design and attacked DDR SDRAM, it took me a good year before it worked the way I wanted.
<sb0>
SDRAM is nasty stuff. but knowing how to make it reliable and fast is a perfect exercise to become good at fpga design.
* ysionneau
fully agrees with all of this
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