lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub68> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/ef32e7aa7a44...569600b607ea
<GitHub68> artiq/master c8f2f4b Yann Sionneau: Add missing __init__.py
<GitHub68> artiq/master 569600b Sebastien Bourdeauducq: frontend/pdq2_client: fix entry point
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<GitHub173> [migen] sbourdeauducq pushed 3 new commits to master: https://github.com/m-labs/migen/compare/6fca1dd4dc4f...754a6324bd7b
<GitHub173> migen/master c0c4c9f Florent Kermarrec: new simplified way to declare submodules/specials/clock_domains...
<GitHub173> migen/master e888e92 Florent Kermarrec: use new submodules/specials/clock_domains automatic collection
<GitHub173> migen/master 754a632 Sebastien Bourdeauducq: no_implicit_submodule -> implicit_submodule
<GitHub61> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/9abb5ebac3b68b62edadc3272aa8896765b1aeaa
<GitHub61> misoc/master 9abb5eb Florent Kermarrec: use new submodules/specials/clock_domains automatic collection
<GitHub23> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/5f5da6f6d5ea458ccb02d8d4d75a18d984b2a52d
<GitHub23> artiq/master 5f5da6f Florent Kermarrec: use new submodules/specials/clock_domains automatic collection
<sb0> _florent_, artiq soc is no longer booting, after this patch it seems
<_florent_> hi sb0, I'm going have a look at that right now
<sb0> yes... it works after reverting
<sb0> I just get a blank line on the UART after the reset, and then it crashes
<sb0> (instead of the BIOS)
<_florent_> Sorry for that, I try to fix that ASAP
<sb0> problem also happens with ppro/BaseSoC
<sb0> (without artiq)
<_florent_> I have done my tests on designs without CPU, it's probably related to CSR, I'm testing investigating on the de0-nano
<sb0> uart_irq gets stuck at 0
<sb0> some csr logic isn't generated anymore, indeed
<_florent_> indeed, I have the same issue on the de0-nano with simple.py, I see the missing logic in the generated code
<sb0> _EventSource probably needs a implicit_submodule = False too
<_florent_> it seems to be the logic of the EventManagers
<sb0> _florent_, why do you "only collect implicit submodules that are not already finalized" ?
<sb0> also r += [(name, submodule.get_fragment())] -> r.append((name, submodule.get_fragment()))
<_florent_> I was just looking at that: are we sure that a module that is finalized if already collected?
<sb0> the problem is that collect_named_submodules should not return the submodules twice
<sb0> _collect_anonymous_submodules clears the submodule list
<sb0> _collect_named_submodules doesn't
<_florent_> but _collect_named_submodules does not use/modify the submodule list
<sb0> yes. and that's why it'll incorrectly return the same modules when you call it again.
<sb0> in the original code, a module can only be collected once
<sb0> and your patch breaks that
<sb0> additionally:
<sb0> 1) we do need a implicit_submodule = False in _EventSource
<sb0> 2) some modules (trying to determine which right now) have the parent module somewhere in their attributes, and thing break
<sb0> #2 sounds like be a pain to fix and enforce
<sb0> hmm, after fixing that it boots further but still crashes in the bios
<sb0> innocent-looking change with tons of bugs...
<sb0> those are the fixes I have right now
<sb0> we might have the #2 problem with clock domains, specials, etc.
<sb0> bah
<sb0> _florent_, care if I just revert the whole thing?
<_florent_> no, do that, I will try to fix it and test it on all the designs I have
<sb0> the fix is complicated
<sb0> and I wonder if implicit submodules are a good idea at all
<sb0> how do you know that some module that two classes set as attribute should be a submodule of one and not the other?
<sb0> hmm do we care?
<_florent_> you don't know
<sb0> maybe just collect all unique submodules, and finalize/get_fragment the set
<_florent_> you just have to collect it once
<_florent_> I'm not sure this is so complicated to fix that, give me 2-3 hours before reverting :)
<_florent_> I'll try to fix that and test on de0-nano/kc705/mixxeo
<sb0> right now one problem is that the top-level is a "submodule" of one of its submodules
<sb0> how to fix that, and all other similar issues?
<_florent_> the top-level is a "submodule" of one of its submodules > can you explain a little bit what you mean?
<sb0> one of the cores has the top-level SoC in its attributes
<sb0> so the top-level is considered an implicit submodule of the core
<_florent_> OK yes that can be problematic, which core is it? (just to have a look)
<sb0> not sure. but migen shouldn't do anything weird in that case anyway.
<sb0> it should be permitted to pass module references all over the place
<sb0> I guess finalize() should not mess with get_fragment() ...
<_florent_> you can do it by setting no_implicit_submodule to True, but this is maybe not practical
<sb0> that will be a mess to use
<sb0> and there will be weird bugs
<_florent_> I agree
<_florent_> you can revert everything, if I have something that fix all the points we discussed together I will re-submit you a patch
<sb0> clock domain renaming also assumes a well defined module hierarchy
<sb0> and well defined location of clock domains - if the same clock domain object ends up as attr in two modules, that's a problem
<sb0> we should have unit tests for all those things...
<GitHub189> [misoc] sbourdeauducq force-pushed master from 9abb5eb to 9bb7e6d: https://github.com/m-labs/misoc/commits/master
<GitHub95> [migen] sbourdeauducq force-pushed master from 754a632 to 6fca1dd: https://github.com/m-labs/migen/commits/master
<GitHub0> [artiq] sbourdeauducq force-pushed master from 5f5da6f to 569600b: https://github.com/m-labs/artiq/commits/master
<sb0> _florent_, guess you need to add the .submodules in the sata core ...
<_florent_> yes...
<_florent_> about collecting thing, what can be done is maybe:
<_florent_> pass the list of the already collected modules/specials/clock_domains to the module we want to finalize
<_florent_> when collecting submodules of module do not collect already collected modules/specials/clock_domains
<_florent_> this way everything should be collected only once and with the right hierarchy, no?
<_florent_> or do you still see hidden cases?
<sb0> no, it won't work
<sb0> let's say we have module X that defines clock domain A
<sb0> module U has foo and bar attributes which are two instances of module X
<sb0> those two instances are also quux and foobar attributes of module V
<sb0> should we have clock domains foo_A and bar_A, or quux_A and foobar_A?
<_florent_> OK I give up :)
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<GitHub59> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/47aa634ab56acacd950ab7c6ee1b754bc4dc532e
<GitHub59> artiq/master 47aa634 Sebastien Bourdeauducq: replace periodic schedule with timed schedule
<GitHub185> [migen] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/migen/compare/6fca1dd4dc4f...7471b2a15264
<GitHub185> migen/master 7471b2a Florent Kermarrec: genlib/crc: use OrderedDict
<GitHub185> migen/master 2175a79 Florent Kermarrec: fhdl/std: add FinalizeError import
<GitHub184> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/9fb42e49529e01974cab3248379aca383aa50231
<GitHub184> artiq/master 9fb42e4 Sebastien Bourdeauducq: doc: use sphinx-argparse
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