Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<paulk-gagarine> mripard_, hey, I'm looking to setup a nanopi neo2 -- I've seen on the list that you already accepted patches for those and merged them, but I cannot find them on https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git/
<paulk-gagarine> mripard_, should I look some other place?
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<plaes> paulk-gagarine: wens has sunxi-next branch in github
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<Net147> plaes: how's the CCU patchset going?
<plaes> Net147: sata is still b0rked
<plaes> and haven't had time to look at it for a month now..
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<plaes> SATA has fixed post divider
<paulk-gagarine> plaes, neat, will look into that
<Net147> plaes: yeah, I still need to wrap my head around how the clock hierarchy works...
<mripard_> paulk-gagarine: we changed of git repo, s/mripard/sunxi/
<paulk-gagarine> mripard_, oh, good to know :)
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<Net147> plaes: the SATA clock registers are being set incorrectly? or not set at all?
<plaes> Net147: I couldn't figure out how to plug in the post-divider
<plaes> SATA clock has multiple parents
<plaes> HDMI patchset included some improvements for multi-parent support
<mripard_> plaes: what's wrong with CCU_FEATURE_FIXED_POSTDIV ?
<plaes> IIRC it was unimplemented
<plaes> SATA is div clock
<mripard_> what do you mean ?
<codekipper> Hi, does anybody know if there is a nighly build for uboot images?
<mripard_> is it a post-divider or a divider ?
<codekipper> just thinking about putting together some instructions for booting arch linux and if there is uboot images out there then no building is required
<jelle> instructions for arch are simple :-)
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<codekipper> yeah I know....thought it maybe useful for others...nightlies seem broken here http://dl.linux-sunxi.org/nightly/u-boot-sunxi/u-boot-sunxi-mainline/u-boot-sunxi-mainline-latest/
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<Net147> mripard_: I guess he is trying to work out how to model a clock based on the formula "parent * N * K / M / 6" or "parent * N * K / (M * 6)"
<vinz0r> what can be done to help mainlining pinebook support?
<jelle> vinz0r: first off, working on the wiki? http://linux-sunxi.org/Pine_Pinebook
<Net147> plaes: how about using SUNXI_CCU_DIV_TABLE for pll_periph_sata_clk?
<vinz0r> jelle, ok I can look into that
<Net147> plaes: just have the .div values multiplied by 6
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<mripard_> Net147: why not N * K / M, with a post-divider of 6
<mripard_> instead of hacking things around
<Net147> mripard_: fixed_post_div is implemented by NK clock, not NKM clock?
<mripard_> then implement it in NKM clocks
<mripard_> plaes: which SATA clock are we talking about, the PLL-SATA or the SATA one?
<wens> if it's the PLL-SATA one, you have to have a common base clock for both PLL-SATA and PLL-PERIPH
<Net147> wens: sata clock is then "base clock / M / 6" or alternatively "base clock / (M * 6)"?
<wens> pll6-base = 24*N*M, pll-sata = pll6-base / M / 6, pll-periph = pll6-base / 2
<wens> Net147: does it matter if you multiply first or not?
<Net147> n / M / 6 is mathemtically the same as n / (M * 6)...
<Net147> A20 manual has (...) / M / 6, R40 manual has (...) / (M * 6)
<wens> so you mean in the clock implementation?
<Net147> not sure, I have almost no experience with clocks...
<Net147> so the question would be how to model "pll6-base / M / 6" using ccu_div
<mripard_> M, with a post-div
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<Net147> so implement new ccu_m clock type?
<Net147> oh it's in ccu_div
<Net147> so I guess implement fixed post-divider support in ccu_div then
<plaes> sry, back from meeting..
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<plaes> Net147: yeah, I couldn't get it working
<plaes> but it was before mripard_ improved the multi-parent clock support
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<Net147> mripard_: are you able to spot any issues there?
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<mripard_> no, but I'm not sure what the issue is
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<Net147> plaes: perhaps there is nothing enabling and setting the SATA clock rate in the DT? A20 manual says clock output should be equal to 100 MHz if the SATA is on
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<plaes> Net147: where do you see the rate ^^
<Net147> plaes: the default values for N, K, M fir PLL6-SATA configure a 100 MHz SATA clock by default which is the rate required for SATA...
<mripard_> plaes: the DT will probably not help you with it
<mripard_> but what is your issue exactly with this clock ?
<plaes> I couldn't get it working unless, I had already enabled it in u-boot
<plaes> but it's been a month I last played with it
<mripard_> yeah, but it doesn't work isn't really a description, it's a statement
<plaes> like I said, I don't remember currently
<mripard_> is clk_set_rate failing? Some other function ?
<Net147> plaes: PLL6 is disabled by default, it needs to be enabled for the SATA clock. perhaps nothing enables PLL6 if SATA is disabled in U-Boot.
<mripard_> is it failing because of what, you try to set a rate and it doesn't returns the proper rate, something else?
<mripard_> if the rate returned in the clock frmaework ( that you can check through debugfs) is the right one, is it consistent with the value in the register?
<mripard_> etc...
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<Net147> I can check the PLL6-SATA register using "devmem2 0x01c20028" for example
<Net147> mripard_: do you use devmem2 for that purpose as well?
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<mripard_> yes
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<nove> discussion of fuchsia and gpl -> https://news.ycombinator.com/item?id=14583566
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<plaes> mripard_, Net147: hah.. it was more stupid ...
<plaes> I didn't have SATA clock in the clocks :(
<plaes> only CLK_AHB_SATA
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<MoeIcenowy> mripard: will patches sent now be only applicable on 4.14?
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