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<chatter29>
allah is doing
<chatter29>
sun is not doing allah is doing
<chatter29>
to accept Islam say that i bear witness that there is no deity worthy of worship except Allah and Muhammad peace be upon him is his slave and messenger
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<MoeIcenowy>
mripard: how can I do experiments on r_ccu to get a frequency?
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<ixnus>
allwinner is not doing
<ixnus>
sunxi is doing
<BenG83>
lol
<ixnus>
there is only one maintainer mripard and wens is his prophet :)
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<wens>
huh?
<KotCzarny>
just sunday funsies
<KotCzarny>
feel free to ignore it ;)
<KotCzarny>
and i should point ixnus to be the one telling others to keep on topic :P
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<plaes>
wens: yeah, we got some spam before...
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<spikebot85>
does anyone know if there a distro that currently supports the banana pro using onboard wifi and the 5" lcd
<spikebot85>
so far I can only find images that support one or the other
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<apritzel>
BenG83: jemk: MoeIcenowy: does anyone have a datasheet of the Samsung K4E6E304ED-EGCE DRAM used on the SoPine (and possibly in the Pinebook as well)?
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<apritzel>
after it came to me that LPDDR of course runs at lower frequencies (the fastest being 533 MHz), I got somehow further in the setup
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<apritzel>
so I was wondering how this single DRAM chip is organised
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<MoeIcenowy>
My SoPine seems to use FORESEE LPDDR...
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<apritzel>
MoeIcenowy: oh, really? The SoPine? Is that one having SPI already?
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<jemk>
apritzel: i don't have a datasheet for them. but did you set the correct delays, i think lpddr is much more sensitive to correct alignment of address/command signals
<MoeIcenowy>
apritzel: I didn't know...
<MoeIcenowy>
and I even do not believe that FORESEE makes DRAM
<apritzel>
jemk: yeah, I am at this at the moment
<apritzel>
the delays seem indeed different
<apritzel>
and the rank and page_size issue were a red herring
<apritzel>
because it simply didn't work, so our row_bits and page_size auto detection fails
<MoeIcenowy>
apritzel: yes with a W25Q128
<apritzel>
reporting back 16 row_bits and 8K page size, which results in 4GB DRAM size, which wraps around to 0 with my 32-bit (FEL-capable) SPL
<apritzel>
I think this whole CONFIG_PHYS_64BIT is seriously broken in U-Boot, but that's another topic ...
<apritzel>
MoeIcenowy: so this is the "production" batch already? And chances are that all future SoPines use FORESEE DRAM as well?
<MoeIcenowy>
I don't know
<MoeIcenowy>
and my LPDDR3 init code only results 1GiB DRAM
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<MoeIcenowy>
apritzel: what's your board's silkprint?
<MoeIcenowy>
my is "Model A Rev B"
<MoeIcenowy>
oh it's the base board
<MoeIcenowy>
my SoPine is "Rev C"
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<montjoie>
wens: did you still own the h8homlet devboard ?
<montjoie>
or anybody here who got it, any recent try to use it ?
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<tllim>
Icenoway's SoPine board is the latest and production version, which is Rev C.
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<tllim>
Apritzel's SoPine is the rev A version which don't have SPI Flash.
<tllim>
I didn't release out the Rev B version.
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<wens>
montjoie: yes, but haven't used it in quite a while
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<apritzel>
tllim: do you have a datasheet for the DRAM chip used on the final RevC SoPine?
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<apritzel>
tllim: also: did the final PCB layout change regarding the DRAM?
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<apritzel>
jemk: OK, worked out the bit delay values from the SoPine boot0, which were indeed quite different, but that didn't help
<apritzel>
next step would be comparing register dumps between boot0 on the SoPine and the Pine64 ...
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<tllim>
There are no major change on SoPine Rev A and C. Added SPI Flash and power LED. The SoPine LPDDR3 PCB layout shoukld be identical between Rev A and C.
<tllim>
About LPDDR3 daatsheet, I will check with vendor.
<tllim>
For SoPone baseboard, the different between Rev A and B are the power connector change and add in eMMC module connector.
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<willmore>
ixnus nailed it.
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<willmore>
What's the SOPINE baseboard use for a power connector? 4.0/1.7?
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<apritzel>
tllim: thanks a lot for the info, so DRAM setup-wise it should be the same then
<MoeIcenowy>
willmore: 2.5mm
<MoeIcenowy>
not 1.7
<willmore>
MoeIcenowy, 4.0/2.5? So, not the one on the OrangePi boards? Bummer. I really like that connector.
<willmore>
I don't see any boards on the wiki that use that. Tons for 4.0mm/1.7mm
<willmore>
Maybe a 5.5/2.5?
<MoeIcenowy>
maybe 5.5/2.5
<MoeIcenowy>
at least not 1.7 at all
<MoeIcenowy>
according to tllim 2.5mm is recommended for 5.0V power
<BenG83>
I can see if Tl can upload the datasheet ;)
<jemk>
apritzel: do you set correct mode registers? in your github tree they are still ddr3-only, that wont fit for lpddr3
<MoeIcenowy>
apritzel: won't you base on my patchset?
<BenG83>
I dont have a original power supply
<MoeIcenowy>
(which adds DDR2 support for V3s integrated DRAM
<BenG83>
so I cant measure the dimensions
<BenG83>
my universal 5V/3A had a connector in the kit that fit
<willmore>
MoeIcenowy, I prefer latching connectors. Also, I prefer 12V inputs and letting the board step that down to the voltages it needs. Feeding the board over some flakey connector a voltage that it actually needs is bad design.
<willmore>
Though, for the sake of simplifying the supply chain, they should make it accept 19V so that common laptop adapters can be used. High voltages mean lower currents for the same amount of power, so that's good for the connectors as well.
<KotCzarny>
common as of today
<KotCzarny>
some time ago common was 16V, and earlier it was 12V
<KotCzarny>
etc
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<KotCzarny>
5V makes it easier for integrating battery i guess
<willmore>
KotCzarny, I guess, if you want to use a linear regulator 5V is useful for 4.1V cells, but that's not a good idea, anyway. :) Better to use a SMPS.
<KotCzarny>
5v is a nice 4xAA
<KotCzarny>
hehe
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<willmore>
I have some little single cell phone charger batteries. They're 2.2Ah or so. If i use the cheap 5V charger, they charge fine. If I use the fancy Samsung 5.5V charger, they overheat and charge really slowly. Guess what kind of charge controller they use? ;)
<willmore>
KotCzarny, that's 6V.
<KotCzarny>
nimh/nicd ?
<willmore>
For Ni cells it would be 4.8V
<KotCzarny>
good enough
<willmore>
But will be 4.4 near EOL.
<willmore>
which is outside of the 5V +/- 10% spec and will make some stuff fail.
<KotCzarny>
yup, but it should be fine for a few months
<willmore>
I'll stick with my 'don't feed a board the voltage it needs over a flakey connector' statement. :)
<KotCzarny>
:)
<willmore>
KotCzarny, might be.
<willmore>
gotta run.. Later!
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<BenG83>
the way the power path is on the PB, the 5VDC in always go through the AXP to PS
<BenG83>
and from PS through a boost converter to 5V
<BenG83>
since that is also needed for the battery power path
<BenG83>
that way even if the inpu DC5V are not really 5V or intermittent you still have proper 5V for USB
<BenG83>
btw, is anyone going to Embedded World in Nuremberg ?
<apritzel>
jemk: I changed para.dram_type to MCTL_CR_LPDDR3 of course, if that's what you meant
<apritzel>
jemk: also I changed ZQ and the frequency
<apritzel>
MoeIcenowy: I kind of lost track of all the floating patches regarding the DRAM driver
<apritzel>
MoeIcenowy: also that's partly work done before you posted something, so I just rebased on top of my other branches which give me ATF or FEL support
<beeble_>
robogoat: if you got one with the same winbond than the other ones, you can do a sector lock. but be aware that these are volatile options and will be reset after a power cycle
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<apritzel>
robogoat: I think eventually we might make the SPI flash "secure-only", so Linux can't access it at all
<apritzel>
and then provide some means of firmware update via UEFI (or another firmware interface)
<apritzel>
alternatively this secure-only property could be turned off for a certain boot, so that the SPI becomes update-able by Linux
<apritzel>
think of some read-only jumper or the like
<apritzel>
robogoat: regarding KVM: what do you mean exactly by "doesn't build kvm by default"?
<apritzel>
robogoat: not enabled in the kernel config? Or no QEMU package available?
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<MoeIcenowy>
OH 4.11-RC IS OUT!
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<apritzel>
MoeIcenowy: not really surprising, isn't it?
<apritzel>
MoeIcenowy: oh btw: do you have an update of your DRAM patches?
<apritzel>
MoeIcenowy: I only found the RFC on the u-boot ML
<MoeIcenowy>
temporarily no
<MoeIcenowy>
but will soon
<apritzel>
OK
<MoeIcenowy>
should be in tody in UTC+8
<MoeIcenowy>
maybe for you it's tomorrow
<apritzel>
I will try to pick some of patches for the time being
<apritzel>
*some of the patches*
<apritzel>
I made the delay compensation configurable as well
<apritzel>
since it no longer simply goes with a certain SoC
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<apritzel>
because we need different delays for the SoPine and the Pine64
<apritzel>
probably the Pinebook as well
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<apritzel>
MoeIcenowy: anyway, so far it boots for me on the SoPine
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<apritzel>
MoeIcenowy: I decided to wait for your post and then post my LPDDR3/SoPine patches on top of that
<MoeIcenowy>
thanks ;-)
<apritzel>
but no hurry on that, I can wait a day or two
<apritzel>
it's not that I get bored ;-)
<MoeIcenowy>
oh I will now make a v7 for H5...
<MoeIcenowy>
finally mripard at least merges H5 ccu
<MoeIcenowy>
hope v7 can be the last version
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<MoeIcenowy>
drivers are all ready, but dts work is left
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