Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<milokim> Hi, can I get RSB (Reduced Serial Bus) details about clock gate and reset line?
<milokim> I've been trying to add RSB DT properties based on mainline kernel v4.5-rc1, but 'clocks' and 'resets' are not clear because I can't find any description in A64 user manual.
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<marble_visions> hi all, after checking from yesterday, it seems that when I set the mmc2 to detect mode 4 (sd card detection controlled from /proc) after i do an echo 1 > /proc/drivers/sunxi-mmc.2/insert, the PIO assignment changes as well
<marble_visions> is this expected behaviour?
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<Seppoz> anyone in here know can/mscan?
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<plaes> mscan?
<plaes> Seppoz: please formulate your question
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<rellla> ssvb: did you experiment with the fb_wait_for_vsync() on h3?
<rellla> found this commit https://github.com/O-Computers/linux-sunxi/commit/d4662ee456eef8873c23f1400c60b93c0ca835eb#diff-a79ca3392c90139441b7b33248c57bebL877 and wonder, if the ioctl works like it does on A10/A20, when readding the fb_wait_for_vsync(info) ?
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<ssvb> rellla: the display driver is different on h3
<ssvb> I added this patch because I wanted to disable vsync, so that it does not hinder lima-memtester
<rellla> ssvb: i know that it's different
<rellla> i just wonder, if we can wait for the next vsync via ioctl?
<ssvb> rellla: the proprietary mali driver expects the FBIOPAN_DISPLAY ioctl to wait for vsync
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<ssvb> if we implement FBIO_WAITFORVSYNC as scheduling "one short" vsync wait on the next FBIOPAN_DISPLAY ioctl, then we can have perfect tear free 3D graphics
<ssvb> if we do vsync waiting directly in FBIO_WAITFORVSYNC ioctl, then it does not work nicely with mali
<rellla> ssvb: i need some mechanism to wait for the next vsync within libvdpau-sunxi's presentation queue
<ssvb> for H3?
<rellla> yes
<ssvb> how do you make the next video frame visible on H3?
<rellla> did not yet dive into it. it's jemk's implementation
<rellla> but i did the presentation thread around it. and to provide correct timestamps for synchronisation within the app, i have to wait for vsync and take the time.
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<ssvb> on A10/A20 the layer configuration updates used to be automatically postponed until the next vsync
<ssvb> does this not work on H3?
<rellla> i think it does, but i need the timestamp to provide synch ability
<ssvb> you can always experiment with patching the kernel
<rellla> ^ this code is an old version though
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<rellla> i will do. i was just curios, if someone did it before :p
<ssvb> yes, on A10/A20 the FBIO_WAITFORVSYNC ioctl was waiting for vsync
<ssvb> btw, I have always used the following video files for testing tearing - https://people.freedesktop.org/~siamashka/files/20130130-tearingtest/
<rellla> *did it on H3 :)
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<plaes> bbrezillon: nice patch spree :)
<bbrezillon> plaes: hehe, and that's not even finished
<KotCzarny> brezilion of patches
<bbrezillon> :)
<plaes> does this mean we are closer to NAND support? :P
<bbrezillon> for the allwinner specific part, yes
<bbrezillon> we're working with Richard Weinberger to patch UBI to make it reliable on MLC NANDs
<plaes> ah.. MLC
* plaes still needs to figure out how to configure second NAND chip on his Gemei G9
<bbrezillon> hm, that should work out of the box
<bbrezillon> I never tested it on a real device though
<bbrezillon> let me know when you want to test it
<plaes> btw, that C.H.I.P - does it use SLC or MLC?
<bbrezillon> it uses an MLC NAND, but operated in SLC mode
<bbrezillon> which means you only have access to half the NAND capacity
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<bbrezillon> but it guarantees the reliability
<plaes> cool, robotics club in local college is planning to use those as platform for sumorobots
<bbrezillon> Richard and I are working on supporting MLC NANDs in MLC mode
<bbrezillon> but this requires changes in the MTD/NAND and UBI layers
<bbrezillon> and we're only starting to test the implementation
<plaes> yeah.. I have seen your slides (from somewhere)
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<slapin> hi, all!
<slapin> is there some preliminary patches for CSI support in mainline kernel?
<wens> nope
<wens> none that have been shared
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<slapin> wens: thanks, then I will have to hack-up something quickly
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<hp197> A20 GPIO/IRQ stability is decent
<hp197> time constant 4, precision 0.001 us, tolerance 500 ppm,
<hp197> 19:29:03 up 11 days, 16:38, 1 user, load average: 0.01, 0.02, 0.05
<hp197> (cubietruck)
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<slapin> hp197: is there some data on A10/A13?
<hp197> slapin: not as far I know of
<slapin> I wonder if I can drive motors directly from it
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<hp197> direct?! no
<hp197> a motor would drain too much power from the mcu/gpio
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<slapin> hp197: no, I mean via driver chip with dir/step of course
<hp197> ok, didnt want to spoil the fun :p
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<hp197> if U have a normal dc motor, then probably a npn tor and one of the analog pins will do (not sure)
<plaes> isn't free-electrons working on CSI for C.H.I.P
<hp197> and if you have a steeper motor, it will all depend on the interface of the driver, but most are i2c or onewire I guess (havent used them that much)
<mripard_> plaes: no (or at least, not yet)
<plaes> ok :)
<hp197> slapin: ^ (forgot to ping)
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<hp197> slapin: /me just remembers that lot of stepper drivers use PWM (arent they?)
<hp197> clock is stable enough to drive pwm, so you should be fine
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<slapin> hp197: most are step/dir
<slapin> hp197: you need to produce pulse on step pin to drive it
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<slapin> hp197: stepper motors are for precise steps when you need control, so just PWM is not an option in my case
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