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<wens>
ssvb: both referencing the same pin? in this case i think you should just have a single vbus regulator, and reference it for both phys
<wens>
otherwise, theorectically you could end up where one regulator is on, and the other is off, and who knows what the state of the pin is actually
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<ddc>
Hi everyone wondering if there is someone here who has some experience with CSI?
<grugly>
I use to watch that tv show..
<grugly>
gibbs and gabby.. I was always a fan of gabby..
<ddc>
I'm trying to implement a driver using v4l2 media controller framework for sun4i (Camera Sensor Interface )
<grugly>
but of course, I figure you are talking about something far more technical, and I've been drinking and am just trolling ;)
<ddc>
grugly: lol
<grugly>
and no, I've never.. and replys are generally slow around here.. kick back and idle for a while.. someone in the know might wake up at some stage..
<ddc>
grugly:different time zone I guess
<grugly>
irs is kinda slowweb...
<grugly>
the buffer stays for a while, and people read it every now and then..
<grugly>
look for the text amongst the parts and quits..
<grugly>
irc even
<ddc>
grugly: I know I'm not expecting a quick reply
<grugly>
excellent :)
<grugly>
I have whitelist perms on an irc server, and I see wpople all the time talk about whitelisting, but they don;t give usernames.. it's so silly..
<grugly>
irc? I meant minecraft.. I watch on irc
<ddc>
grugly: I would like to discuss some ideas and I thought irc maybe usefull for that
<NiteHawk>
it is. if you get in touch with people, it's a rather direct and immediate way to communicate. the thing is you just can't expect folks to be "available" 24/7
<ddc>
NiteHawk: I'm not expecting anything
<wens>
grugly: that's ncis :p
<NiteHawk>
ddc: i wasn't referring to you specifically, just talking in general
<wens>
ddc: mainline?
<ddc>
wens: yes
<wens>
cool, was looking into it, but very low priority for me
<wens>
iirc the controller is very simple
<wens>
cameras on the other hand, not so simple
<wigyori>
morning
<ddc>
wens: I'm trying to mimic the OMAP 3 ISP structure. which seems to fit nicely with A33/A80 but not sun4i
<ddc>
wens: I've some issues now in how to make the driver as univeral as possiple i.e works for all sunxi family
<wens>
ddc: i think you should focus on the simplest implementation, like csi1 on A10/A20
<wens>
then extend it for csi0
<wens>
that was my plan anyway
<wens>
the A33/A80 ones seem to have an extra mux, so the registers don't line up correctly
<ddc>
unfortunately I only have CSI0 available in my dev board.
<wens>
ah, well, csi1 is like a dumbed down csi0, no multiple channels
<ddc>
The muxex can be part of the physical interface entity
<wens>
what hardware do you have?
<wens>
i would just focus on getting a simple soc_camera driver working with a single format first
<ddc>
I've two custom boards with A20 and A33
<wens>
and not overthink or over-engineer it from the beginning
<wens>
do you also have a supported camera?
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<ddc>
wens: that is ok but I found that the media controller is more suited than the camera_soc framework
<wens>
the user manual only mentions writing to memory
<wens>
and we have no official docs for the video engine or ISP
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<wens>
imho media controller seems a bit overkill
<ddc>
wens: I'm aware of that. but looking at the A10 user manual ISP FE can be linked to the CCM of the CSI and can source it is output to SRAM/DRAM
<ddc>
wens: overkill why?
<wens>
ah, wasn't aware of that. So you can use camera -> CSI -> DRAM, or camera -> CSI -> ISP -> DRAM
<ddc>
I guess. And you can then implement the ISP as a seperate entinty and link to the pipeline
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<ddc>
s/entinty/entity
<wens>
about overkill, what i meant was media controller seems to want to solve dynamic discovery and configuration of the media related blocks
<wens>
but with DT and relatively simple hardware, is there such a need for us?
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<wens>
anyway, i just thought using soc_camera is easier if we don't have to support ISP
<ddc>
You have a point if we only dealing with CSI1 but with CSI0(two pipeline) and other SOC which have more compicated bus interface then the story is different
<ddc>
s/compicated/complicated
<grugly>
but compicated is cute..
* grugly
gives ddc a stuffed toy to play withj
<wens>
by 2 pipeline you mean the ISP right?
<ddc>
yes
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<wens>
the manual doesn't even say which channel gets sent to the ISP lol
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<wens>
i'm out of ideas. this turned out to be more complicated than i thought
<ddc>
Look at the ISP Mode register (INPUT_FMT)
<wens>
doesn't say much, 9:8 bayer_seq, 0: input_fmt
<wens>
A10 user manual v1.5 btw
<ddc>
0:Bayer Raw, 1:YUV422
<ddc>
Which I guess can tell what channel to use
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<wens>
or non-CCIR656 modes in CSI0 imply only 1 channel
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<engideavr_>
Hello, I have an Olimex A20 board and would like to ouput a clock to clk_out_a_pins_a , may I ask a question here ?
<engideavr_>
Currently on a running Linux version 4.3.0-rc1-96427-g904c778-dirty, playing around with sun7i-a20-olinuxino-micro.dts but not much luck on results..
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<wens>
engideavr_: the clk needs a user to activate it
<wens>
the pinctrl setting (which is handled by the driver core) only muxes the pin, it doesn't enable the clk
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<engideavr_>
wens: I have &clk_out_a { in the olimex dts and pinctrl-0 = <&clk_out_a_pins_a>; status = "okay"; just like the uart code, what am I missing ?
<wens>
and what device is that supposed to be?
<wens>
clk usage is not automatic, the device driver has to use it
<wens>
say a device driver is expecting one clk, it will not touch the second one you added yourself to the dts
<wens>
and the majority of clks on sunxi aren't devices, they're just clocks
<wens>
so doing what you did does nothing really.
<engideavr_>
So, I have somewhat to "open" the clk_out_a ?