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<pk>
i am very confused about AXP209's dcdc2 as per data sheet it does not have a default voltage and can only be set by I2C..but it is supposed to provide VDD-CPU ..i dont understand this cyclic dependency..how would cpu run without VDD-CPU and how would DCDC2 output will be programmed without running cpu?
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<pk>
can someone clarify this?
<gzamboni>
it has some default settings for the bootup in the BROM
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<gzamboni>
also when the axp is powered off and turned back on it should get a default good value for the allwinner cpu so the brom can set up the rest of the values. this is afaik
<gzamboni>
i know there are some axp i2c comunications in the brom
<libv>
icnova board and baseboard are supposedly in the post, with some luck, i get it tomorrow around noon
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<NiteHawk>
libv: keep us posted on how things go with that :)
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<libv>
NiteHawk: that statement is compeltely superfluous :p
<libv>
you know that i will not shut up about this :p
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<NiteHawk>
oh, really? :D
<libv>
unless they really are on the level
<libv>
which would be boring and not fun
<NiteHawk>
which seems somewhat questionable
<vpeter>
libv: Will there be any post somewhere to read the adventure?
<libv>
i do have high hopes that i would have to escalate this and even find a german ip lawyer, and figure what steps really need to be taken when there actually is an opportunity for changing things through lawyers
<libv>
vpeter: again, i am not known for my silence when lash on to something
<pk>
gzamboni: axp209 datasheet says"After power on, DC-DC and LDO will be soft booted in a preset timing sequence, and then either the
<pk>
Host or PWREN the pin can enable/disable power"
<pk>
so basically for sometime the dcdc2 will remain 1.2v or so and during that time CPU can run the BROM code and configure according to requirement
<pk>
am i right?
<vpeter>
libv: Yes, I do already know that. But woudd be nice to read whole story you will made. Like how things go from first contact on.
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<gzamboni>
i think so, in some of the sdks we have there is the brom egon code.
<libv>
vpeter: first i evaluate what i get sent, then i send a nice email requesting access to the gpled software provided with this product
<pk>
gzamboni: BROM is hardcoded in cpu so i guess it shouldn't have code related to axp209..boot0 or boot1 (which are written by us) should initialize axp209 right?
<pk>
if that code is in BROM , how can cpu presume that axp209 is used and not some othe power ic
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<gzamboni>
afaik the boot1 and boot0 are the bootloader code, the one hardcoded in the allwinner ic.
<pk>
gzamboni: If we agree that allwinner cpu has some hardcode which can initialize axp209..but then problem is how can A20 chip assume that itwill always be powered using AXP209 only?
<gzamboni>
dont know, you will have to study their code to discover that
<NiteHawk>
pk: i've been taking a quick glimpse at the A20 case. it seems vdd-cpu is not the only supply for the cpu, there's also vdd-sys - the banana pi schematic (which should be more or lesse a reference design) shows vdd-sys to be connected to dc-dc3
<NiteHawk>
and dc-dc3 on the axp209 has a configurable "startup" voltage level
<pk>
NiteHawk: yes i thought about it earlier but that would mean noly VDD-SYS is necessary to run the bootloaders? and not the VDD-CPU?
<wens>
whatever the default voltage may be, it is enough to drive the SoC at the default frequency (24MHz)
<wens>
so probably 1.0V, the lower bound of the recommended parameters
<pk>
wens: that does not make sense ..it should be something definite AXP is supposed to be a chip to be used for any SoC not just A20 right?
<wens>
first thing boot0/SPL would do is talk to the PMIC and raise the voltage
<NiteHawk>
pk: i'm not familiar with the details of the soc startup process. but if we assume that initially vdd-cpu is unavailable, then it seems logical that vdd-sys would be sufficient to somehow get the bootstrap "up and running"
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<wens>
pk: it is likely designed to be partnered with A10/A13/A20
<gzamboni>
afaik allwinner started doing only the axp and after they got into the arm microcontroller stuff
<gzamboni>
so yes, it should be usable into other devices
<pk>
wens: lower bound for DCDC2 is 0.7 but lower bound for VDD-CPU is 1.0
<wens>
pk: i said a reasonable default for DCDC2, which might not be its lower bound setting
<pk>
ohh i see
<pk>
that makes sense
<wens>
the datasheet doesn't say, so if you really want to know, you'll have to rip out one and test it yourself, or ask X-Powers
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<pk>
wens: actually the datasheet says that DCDC2 will do a softstart on powerup i.e. a voltage ramp of 1.6mV/us
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<wens>
but it does not say the target voltage, does it?
<pk>
no that is the problem :P
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<pk>
NiteHawk: you argument is most convincing..probably only VDD-SYS is required for doing some low level stuff like running BROM/FEL Mode/boot0/boot1 and from there boot0 and boot1 can configure axp209
<NiteHawk>
i could image that the soc maybe has internal means to run the vdd-cpu off vdd-sys, if the external supply is missing / insufficient? but so far i was unable to find any documentation on this. at least the bpi schematic has an explicit 1.4v test point for "intvdd" from dc-dc3, and that directly feeds vdd-sys
<pk>
yes its same in all boards
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<NiteHawk>
dc-dc3 can be hardwired for its's default voltage level by DC3SET (see datasheet 9.6 The default voltage/Start timing settings)
<pk>
DC3SET pin is kept floating so that its default voltage is set to 1.2 and then DCDC3 is used for VDD-SYS ..but still nothing conclusive about what VDD-SYS and VDD-CPU do inside the chip
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<ssvb>
pk: hmm, that's an interesting point about DCDC2
<oliv3r>
anybody actually using sunxi-next with nand support etc?
<ssvb>
pk: in practice, when A20 is paired with AXP209, the DCDC2 voltage is set to 1.25V at start, the DCDC3 voltage is set to 1.2V and the CPU clock frequency is 384MHz
<ssvb>
pk: I have measured the voltage on several boards, so this is a kind of experimental observation
<philectro>
salut les geeks
<ssvb>
pk: maybe AXP209 does have a reset default for DCDC2 (just like for DCDC3 with the DC3SET pin), but it is not documented
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<ssvb>
pk: or maybe we need to look at the BROM code more carefully and check whether it tries to configure AXP209 in any way
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<ssvb>
pk: still, I would assume that whoever has designed the reference schematic for A10/A20 + AXP209 devices, must have taken care of ensuring a sane reset default for the DCDC2 voltage
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<ssvb>
wens: regarding the default DCDC2 voltage in AXP209, the english version of the AXP209 says "The AXP209 provides customizable default voltage settings of each power supply and start up timing" and "For more information, see “The default configuration instructions” section"
<ssvb>
wens: but there does not seem to be any section named “The default configuration instructions”
<ssvb>
wens: is the Chinese version of the AXP209 manual more detailed?
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<wens>
nope
<ssvb>
wens: also the "10.5 REG 12H:Power Output Control" register description says that "The default value: XXH"
<ssvb>
wens: if we interpret it as "undefined", then the "DC-DC3 Switch Control" may be either "0:Shut down" or "1:Turn on"
<ssvb>
wens: which kinda defeats the purpose of having the DC3SET input pin for configuring the default voltage
<ssvb>
wens: could it be that "The default value: XXH" statements mean that the register value is very likely defined, but just not documented? :)
<ssvb>
wens: we can probably dump the values of all the AXP209 registers after reset and document them in the wiki, then check if they make some sense
<wens>
ssvb: the later makes more sense
<wens>
you would have to do that in SPL though
<wens>
before any voltages are set
<ssvb>
yes, of course
<ssvb>
having a more complete and less ambiguous documentation from the vendor would have been even better :)
<ssvb>
people have started gradually cleaning up the fallout, caused by your u-boot-sunxi repository default branch change ;)
<ssvb>
there are probably a few more places, which require similar changes in the linux-sunxi wiki and in various thirs-party blog posts and tutorials
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<oliv3r>
ssvb: who is 'bur'
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<ssvb>
oliv3r: I have no idea, but this person is probably the first victim who has been hurt by this problem and decided to make things easier for the others
<oliv3r>
which reminds me, i should write a porting guide and send out e-mails to people to port their boards
<ssvb>
this sounds like a good idea to me
<oliv3r>
time is not on my side!
<libv>
ssvb: that and should've been surrounded by '_'
<libv>
that "and" even
<libv>
because it is relatively rare that people do that
<libv>
making all the more laudable that bur, whoever he is, did so
<libv>
+it
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<wens>
ssvb: hmm, the dcdc default settings might also be factory customizable, meaning if you want a custom batch, you can get them?
<ssvb>
wens: that's a plausible theory too
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<topi`>
anyone with A20-OLinuxino-Lime2 board here? does it work with mainline? I'm mostly interested in SATA
<topi`>
it would make a great board for a small NAS
<topi`>
I guess the A20 is one of the better-supported allwinners
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<TheLinuxBug>
tomboy64
<TheLinuxBug>
er
<TheLinuxBug>
topi`: I have had decent success with BananaPi A20 and a NAS I have been deving
<topi`>
what's the max speed off of a disk on an A20 device? the SATA must be rated-limited, right?
<TheLinuxBug>
I tested with port multiplier software raid you can get about 25M/sec write/80M/sec read max in that config, I am soon to test a SYBA card with built on raid chip to see the difference there
<TheLinuxBug>
the specs say
<topi`>
it's not very important, but being capped at 480Mbit/s just sicks
<topi`>
sucks
<TheLinuxBug>
45Write/200Read
<TheLinuxBug>
I say
<TheLinuxBug>
with single disk
<topi`>
ok
<TheLinuxBug>
you can get read of 80-90
<TheLinuxBug>
and write is 45M/sec
<TheLinuxBug>
about
<topi`>
it's enough if it saturates the gigabit ethernet :)
<TheLinuxBug>
more like 40M
<TheLinuxBug>
the bottleneck is usually the network card
<topi`>
yeah
<TheLinuxBug>
you need to pin it to cpu2
<TheLinuxBug>
and even then can only max 50M/sec
<TheLinuxBug>
so
<TheLinuxBug>
if you do test it
<TheLinuxBug>
let me know
<TheLinuxBug>
I have a list of tuning stuff
<TheLinuxBug>
you might like to know
<topi`>
oh, the cortex-a7 @ 1ghz on the A20 is the limiting factor?
<TheLinuxBug>
the fastest network storage method to use will be samba
<TheLinuxBug>
you can get your 40/40 pretty much
<TheLinuxBug>
yeah the irq for the nic on BPi at least can only use 1 core
<topi`>
I thought it would be just fine to pick a slower cpu for the disk I/O but :)
<TheLinuxBug>
I am would assume limex would be similar
<TheLinuxBug>
but maybe different nic?
<TheLinuxBug>
remember BPi has gigabit
<TheLinuxBug>
not sure what olinex has
<TheLinuxBug>
olimex*
<topi`>
it's quite natural the nic can only use 1 core, there is no parallelismi there
<topi`>
the network code is fairly serial
<topi`>
the newer LIME2 olimex has gigabit as well (realtek)
<TheLinuxBug>
ahh nice
<TheLinuxBug>
well hopefully when post gets here tomorrow
<TheLinuxBug>
Iw ill be testing 5x2TB SATA 3.0Gbps drives on SYBA 1:5 port mult with raid, will be in raid5 on BananaPi (A20)
<TheLinuxBug>
will report back the throughput
<TheLinuxBug>
I am hoping to see at least a bit of improvement in writing
<TheLinuxBug>
if I can get 40/40 with raid I will be satisfied
<TheLinuxBug>
I have wired up power off single 180Watt power supply to supply all drives, port mult and BPi
<TheLinuxBug>
pretty nice deal should post pics
<TheLinuxBug>
long and short if its for home use it should be decent for you regardless the configuration you choose.
<TheLinuxBug>
if you expect to use it with a bunch of users or business like enviroment
<TheLinuxBug>
it will fail
<TheLinuxBug>
it won't keep up
<TheLinuxBug>
but imo its better than a usb drive pliged into your wireless router
<TheLinuxBug>
plugged*
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<topi`>
TheLinuxBug: I'm going to order a 18A 5V power supply from dx.com to handle a bunch of OLinuxinos and 2.5" HDDs
<topi`>
I need to create some kind of octopus wiring for them
<topi`>
(the 2.5" HDD will be fed from the SATA power connector on board)
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<TheLinuxBug>
yeah
<TheLinuxBug>
I am using 2.5" drives which is why I am using a regular power supply
<TheLinuxBug>
the BPi will run off the 5v rail on regular molex
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<TheLinuxBug>
with 2.5" drives and only needing 5v could definently work how you are suggesting
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