<wpwrak>
eintopf: heya ! you know how developers calculate time ... given an estimate of X, add one, them multiply by two, and convert to the next higher unit
<wpwrak>
eintopf: so if i say "i'll review it tomorrow", that really means in about four weeks :)
<eintopf>
it's ok
<eintopf>
i made now the "easy to review trivial cleanup patchstack"
<eintopf>
maybe you can review this
<eintopf>
then I add your Acked, Reviewed
<eintopf>
then netdev
<eintopf>
my internet is damn slow today
kilae has quit [Quit: ChatZilla 0.9.90.1 [Firefox 24.0/20130910160258]]
<eintopf>
first the contiki stick, then two of your atusb which controlled via qemu
apelete has joined #qi-hardware
wej_ has joined #qi-hardware
<apelete>
Hello there
<kristianpaul>
Hi :)
wej has quit [Ping timeout: 264 seconds]
<apelete>
larsc mth: added some logging in ep_config_from_hw() in musb_core.c where the usb endpoints scanning happens -> http://paste.debian.net/60583/
<apelete>
kristianpaul: Hi :)
<apelete>
larsc mth: turns out the scanning is failing on the first musb_read_fifosize() call in there:
<apelete>
musb_read_fifosize() in turn calls musb_readb(), which fails.
<apelete>
seems pretty bad since musb_readb() is trying to read hardware registers, if I'm not mistaken
<apelete>
larsc mth: is possible the something may be missing or badly declared in platform data for the registers not to be readable ?
<mth>
is the udc clock running?
<apelete>
how do I check that ?
<mth>
there is a register that contains the mask bits for all the clocks; printing the contents of that register should tell you whether it's enabled or not
<mth>
clock gate register iirc
<apelete>
ok, in the init function I'm doing:
<apelete>
clk = devm_clk_get(dev, "udc");
<apelete>
int ret = PTR_ERR(clk);
<apelete>
if (IS_ERR(clk)) {
<apelete>
dev_err(dev, "Failed to get clock: %d\n", ret);
<apelete>
return ret;
<apelete>
}
<apelete>
glue->clk = clk;
<apelete>
clk_enable(clk);
<apelete>
<apelete>
thought that was enough to get the clock running
<apelete>
will check the register you're talking about
<mth>
there was something about clk_enable being replaced in recent kernel versions
<mth>
larsc will know more about it
<mth>
I don't know if clk_enable won't work anymore or is just wrong in theory
<mth>
that fragment looks ok, but it's useful to double check, just in case the enable failed, the code gets executed in an unexpected order, something disabling the clock after it got enabled etc
<apelete>
ok, couldn't find out how to check clock gate register so will start by adding checks for clk_enable in case it fails during init
<mth>
simply casts its address to an unsigned int * and dereference that
<mth>
address being the virtual address of the register, which is 0xB.......
<mth>
physical address is 0x1......., add 0xA0000000 for kseg1
<apelete>
mth: not sure about what you're saying. should I cast the return value of devm_clk_get() ?
<mth>
no, the address from the programming manual, inside the musb endpoint scanning code
<apelete>
ha
<apelete>
ok, will look into the programming manual and try to do that from inside the musb endpoint scanning code
porchaso0 has joined #qi-hardware
<apelete>
mth: found it:
<apelete>
The Clock Gate Register (CLKGR) is a 32-bit read/write register that controls the CLOCK GATE
<apelete>
function of peripherals. It is initialized to 0x00000000 by any reset.
porchao has quit [Read error: Connection reset by peer]
<apelete>
the udc bit seems to be 11th bit according to programming manual
porchaso0 has quit [Ping timeout: 265 seconds]
pcercuei has quit [Ping timeout: 260 seconds]
pcercuei has joined #qi-hardware
pcercuei has quit [Ping timeout: 245 seconds]
jekhor has quit [Ping timeout: 240 seconds]
pcercuei has joined #qi-hardware
<apelete>
mth: ok now, I added the folloqing lines at the beginning of ep_config_from_hw():