sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0>
nevermind that some of those SDRAM components are created in SDRAMCore and others in soc/sdram.py, for no reason at all, and configured by a structure defined in the controller cores
<sb0>
_florent_, importing all sorts of random stuff (migen etc.) via misoc.com.liteethmini.common is dirty
<sb0>
god you even import the math module from the python standard library using it
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<sb0>
actually why bother with manual imports at all, we should have a script that scans all the python search path and imports * from every .py file it finds
<sb0>
why is it the "core" part of the verilator simulation modules that does system tasks like creating tun interfaces and ptys?
<sb0>
the simulator should do those system tasks, not the 'user' code ...
<sb0>
and certainly not communicating over hardcoded temporary files
<sb0>
urgh
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<GitHub166>
[misoc] sbourdeauducq pushed 1 new commit to new: http://git.io/vnFIV
<GitHub166>
misoc/new 75ef2f9 Sebastien Bourdeauducq: fix most imports
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<whitequark>
sb0: btw, binutils fully merged
<whitequark>
given how obtuse it is, I'm not sure if we should switch install instructions to address binutils git. better just wait until next release, perha
<whitequark>
rjo: neat. why don't the DSP run faster than that?
<whitequark>
is it limited by propagation delay or something?
<rjo>
it should be a matter of luck whether anything works down there. carriers are frozen out and are only created by field ionixation. thus your carrier density depends on geometry and not on temperature anymore. we have also seen e.g. analog muxes work at cryogenic. but bipolar stuff generally fails.
<whitequark>
i see
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