sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0_> rjo, what is using get_constants()? should there be a misoc patch as well?
<sb0_> I would implement fhdl.Constant differently. forbid int/bool in the "ast", have the operators and eq() encapsulate them before storing them
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<sb0__> rjo, CSRConstant deriving from Constant is somewhat weird. the other CSRs do not derive from Signal ...
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<GitHub38> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/vZUdt
<GitHub38> migen/master 94a2499 Robert Jordens: AutoCSR: refactor common gatherer code
<GitHub124> [migen] sbourdeauducq created new (+2 new commits): http://git.io/vZUdG
<GitHub124> migen/new dec2e23 Sebastien Bourdeauducq: Remove code that will be into MiSoC or other packages.
<GitHub124> migen/new f1dc008 Sebastien Bourdeauducq: Simulator will be rewritten
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<travis-ci> m-labs/migen#73 (new - f1dc008 : Sebastien Bourdeauducq): The build has errored.
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<travis-ci> m-labs/migen#72 (master - 94a2499 : Robert Jordens): The build passed.
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<GitHub119> [misoc] enjoy-digital pushed 6 new commits to master: http://git.io/vZkl9
<GitHub119> misoc/master 35e3853 Florent Kermarrec: move litepcie to a separate repo (https://github.com/enjoy-digital/litepcie)
<GitHub119> misoc/master bbeb8a4 Florent Kermarrec: move litescope to a separate repo (https://github.com/enjoy-digital/litescope)
<GitHub119> misoc/master e49a3c2 Florent Kermarrec: move litesata to a separate repo (https://github.com/enjoy-digital/litesata)
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<cr1901_modern> _florent_: I'm reading the message you sent to the mailing list recently. Is a simulation entering an infinite loop always a bug in the simulator?
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<larsc> if you have a combinatorial loop there is not much the simulator can do
<cr1901_modern> Yea, that's true. I'm asking b/c I have a simulation stuck in an infinite loop, but am having trouble diagnosing it.
<larsc> well, you probably have a combinatorial loop ;)
<cr1901_modern> FWIW, changing one self.comb to self.sync fixes the loop, so you're most likely right. I would just like to know the "why" in addition to the "what"
<larsc> I think with iverilog you can do ctrl+c and then enter the finish command in the interactive mode
<larsc> that allows you to abort the simulation
<cr1901_modern> Python3 captures ctrl+c :( (using Migen simulation b/c idk how to fake the VPI without Migen running)
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<mithro> so - It looks like there is some major migen/misoc restructuring going on?
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<_florent_> cr1901_modern: you can create infinite loops deliberately, but here the issue is when simulating large designs, it's difficult to avoid that with the way migen generates verilog
<_florent_> I have a workaround in my migen fork (from david c) but that's not the right way to do it
<_florent_> sb0 is going to add python simulation of fhdl and only use iverilog when there is a verilog or vhdl instance that needs to be simulated with a simulator
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<cr1901_modern> Will the VPI code be kept for other simulators?
<_florent_> vpi only exists for icarus no?
<cr1901_modern> I thought all simulators were supposed to support VPI
<_florent_> yes, but for now icarus is the only simulator supported by migen
<cr1901_modern> ahhh, see I thought verilator was also supported
<_florent_> verilator is supported, but it's not using vpi, it's simulating the whole SoC at the top level
<cr1901_modern> Hmmm... maybe I should see if I can crash verilator with my design. Still have infinite loop that I can't find :/
<cr1901_modern> I think the infinite loop is happening in imported Verilog code
<cr1901_modern> _florent_: what's different about the link you sent me compared to what's already in the main repo?
<_florent_> there is a workaround to avoid infinite loops
<mithro> _florent_: Have you/sb0 documented the proposed new misoc structure anywhere? I only see 2 emails to the m-lab mailing list?
<_florent_> that's more a discussion, but we will probably remove the topics I created some month ago and add the features rjo was suggesting
<_florent_> the idea is to stabilize migen API, move some things from migen to misoc, cleanup/reorganize misoc and add more tests to ease regression testing and eventually add travis-ci to misoc
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<cr1901_modern> _florent_: I just discovered the display_run parameter
<cr1901_modern> It tells me which combinational statements are running and causing the loop
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<GitHub131> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/vZtOV
<GitHub131> misoc/master 40f47f4 Florent Kermarrec: create liteethmini and move liteeth to a separate repo (https://github.com/enjoy-digital/liteeth)...
<cr1901_modern> yay, liteethmini should be useful to me at some point... for mini FPGAs I presume :P
<_florent_> you will maybe have a non-mini FPGA board at some point :)
<cr1901_modern> Yes, at some point. But I also enjoy the challenge of working with smaller micros/FPGAs
<_florent_> which board(s) do you have?