00:22 <cr1901_modern> This is a stupid question, but... do USB 3.0 ports speed up USB 2.0 device transfers at all?

02:25 <mithro> cr1901_modern: USB3.0 are 100% compatible with USB2.0 devices

02:26 <mithro> Has anyone thought about maybe adding https://github.com/zylin/zpu as a softcore?

02:52 <cr1901_modern> That would be good for smaller projects (although currently, I just embed a 65xx core since the asm's easy to write)

03:05 <cr1901_modern> mithro: I thought so. Just found it odd that one USB port is faster on my laptop than another (I don't have any 3.0 devices)

03:10 <mithro> cr1901_modern: the main interest is it is well supported by the ZPUino project

08:06 <cr1901_modern> sb0: Is the default behavior of the wishbone SharedInterconnect interface in Migen to lock up if there's no match in the address decoder?

08:06 <cr1901_modern> lock up == the master waits forever for an ack that never arrives

08:10 <cr1901_modern> (of course I don't deliberately try to decode invalid addresses, but it seems rather extreme for the whole system to lock up on a bad decode)

22:23 <GitHub152> [artiq] jordens pushed 1 new commit to master: http://git.io/vZUWE

22:23 <GitHub152> artiq/master 01416bb Robert Jordens: copyright: claim contributions...