sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<sb0> cr1901_modern1, it is. fixed now. thanks!
<GitHub26> [migen] sbourdeauducq pushed 1 new commit to new: http://git.io/vZjgY
<GitHub26> migen/new f5ab734 Sebastien Bourdeauducq: fhdl/verilog: fix case value sort
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<GitHub179> [migen] sbourdeauducq pushed 3 new commits to new: http://git.io/vneIK
<GitHub179> migen/new 0b9c672 Sebastien Bourdeauducq: doc: Constant
<GitHub179> migen/new 74c9159 Robert Jordens: add unittests for Constant
<GitHub179> migen/new fd88b9b Sebastien Bourdeauducq: test/constant: use new API
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<cr1901_modern1> sb0: Ack. Np!
<cr1901_modern1> I couldn't actually create working register selectors while that was broken
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<GitHub124> [migen] sbourdeauducq pushed 4 new commits to new: http://git.io/vneMH
<GitHub124> migen/new 6569c51 Sebastien Bourdeauducq: test: bit reverse
<GitHub124> migen/new 9dd3200 Sebastien Bourdeauducq: fhdl/structure: fix namespace pollution
<GitHub124> migen/new 0a92e34 Sebastien Bourdeauducq: fhdl/bitcontainer: remove fslice and freversed
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<cr1901_modern1> sb0: While I'm finding bugs, WaitTimer is also broken in the new branch: bits_for is not defined
<cr1901_modern1> (Yes, I can implement it myself. Just porting old code to test something)
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<sb0> rjo, what do you use fiter for?
<GitHub90> [migen] sbourdeauducq pushed 9 new commits to new: http://git.io/vnvcr
<GitHub90> migen/new c2109f8 Sebastien Bourdeauducq: minor bugfixes
<GitHub90> migen/new bcf6299 Sebastien Bourdeauducq: fhdl/bitcontainer: remove fiter
<GitHub90> migen/new 776579f Sebastien Bourdeauducq: fhdl/structure: all case statements should be lists
<sb0> cr1901_modern1, thanks, fixed
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<cr1901_modern1> sb0: I'm studying your sim code now. Is the generators parameter your way of implementing simulation over multiple clock domains?
cr1901_modern1 is now known as cr1901_modern
<cr1901_modern> Also, I'm really sorry in advance lol. I really am: https://github.com/m-labs/migen/issues/20#issuecomment-141076460 I'm simply trying to create a tristate where each bit in the Signal can have its direction toggled.
<cr1901_modern> The gist in the link is the stripped down version that shows that what I'm trying to accomplish is difficult in Migen :/
<sb0> individual directions are not supported
<sb0> create multiple smaller signals
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<kristian1aul> mithro: oh its yours?
<kristian1aul> actually not
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<rjo> sb0: i can envision it being useful in a couple situations. and it is an important part of the python api if you want to mimick containers.
<mithro> kristianpaul: yes, I designed the Opsis board and Numato built it
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<cr1901_modern> sb0: I did create multiple smaller signals. I think this is a Cat() issue, not a Tristate issue
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