01:58 <mithro> sb0: what was the point of flattening the core structure?

02:02 <sb0> https://github.com/m-labs/misoc/issues/17

02:05 <mithro> sb0: I was looking at how to make it possible to build misoc with all the code being read only

02:06 <mithro> sb0: at the moment it is *really* hard to do that as compile objects and generated headers end up in the misoc tree

02:06 <sb0> yes, that should change

02:08 <mithro> sb0: great!

02:09 <mithro> sb0: you guys are really weird - you use github issues for discussion and then the mailing list for patches!? That is like the total opposite of most groups I know :P

02:11 <mithro> sb0: I'm also looking at how we need to patch the Xilinx tools to get reproducible firmware generation

02:23 <mithro> sb0: I created https://github.com/m-labs/misoc/issues/19 just to call out that goal, I'm pretty sure it sounds like you'll end up doing it as part of #19

02:24 <mithro> sb0: I also closed https://github.com/m-labs/misoc/issues/5 as it was already done and doesn't make sense anymore

02:37 <sb0> http://www.gowinsemi.com.cn/en/productsShow.aspx?n_id=347

03:06 <sb0> whitequark, how do you always find stuff like this? https://twitter.com/whitequark/status/646877714687897600

03:09 <sb0> btw I found this Feynman lecture series very interesting https://www.youtube.com/watch?v=eLQ2atfqk2c

03:26 <sb0> _florent_, ysionneau, why do banks have a CE signal in minicon?

03:27 <sb0> which is stuck at 1

03:27 <whitequark> sb0: I seem to have a penchant for it, somehow

04:51 <mithro> whitequark: The comparison is pretty apt, both topics attract crazies who have NFI about it but speak with authority on it :P

05:23 <sb0> _florent_, why does minicon have to know anything about l2?

05:24 <sb0> https://github.com/m-labs/misoc/blob/master/misoclib/mem/sdram/core/minicon/__init__.py#L62

05:24 <sb0> that's not ok

05:26 <mithro> sb0: I wish someone would just create an FPGA which has high speed SERDES on all the pins

05:26 <sb0> how high?

05:27 <mithro> sb0: ~3.0Gbps would be good (with then a bunch at ~6Gbps)

05:31 <sb0> why on earth make the refresh module from lasmicon optional?

05:31 <sb0> implementing refresh is mandatory for sdram controllersa

05:31 <sb0> -a

07:43 <sb0> mithro, are you using LASMI for SDRAM, and plan on still using it?

07:46 <mithro> sb0: I think we are - https://github.com/timvideos/HDMI2USB-misoc-firmware/blob/master/targets/opsis_base.py#L13 ?

07:49 <sb0> mithro, ok. the sdram unittests are pretty crappy right now. are you interested in improving them?

07:49 <mithro> sb0: interested, yes - have the time too, probably not

07:49 <mithro> sb0: I know _florent_ was interested in reworking the DDR stuff

07:50 <mithro> he has some ideas after getting DDR3 working on the Spartan-6 and something about a "quarter rate DDR" that I didn't really understand

08:05 <GitHub183> [misoc] sbourdeauducq pushed 3 new commits to new: http://git.io/vnMpC

08:05 <GitHub183> misoc/new 0f410e4 Sebastien Bourdeauducq: cores directory

08:05 <GitHub183> misoc/new 9b08b03 Sebastien Bourdeauducq: break down sdram, improve consistency of core names

08:05 <GitHub183> misoc/new ecdc410 Sebastien Bourdeauducq: lasmicon: enable refresh at all times

08:12 <GitHub189> [migen] sbourdeauducq pushed 1 new commit to new: http://git.io/vnMjj

08:12 <GitHub189> migen/new af88a7a Sebastien Bourdeauducq: setup: simpler version check, beta status

08:14 <travis-ci> m-labs/migen#109 (new - af88a7a : Sebastien Bourdeauducq): The build passed.

08:14 <travis-ci> Build details : https://travis-ci.org/m-labs/migen/builds/81922716

10:04 <mithro> sb0: Sadly my day job doesn't pay enough that I can afford to get _florent_ to work on my things full time :(

10:13 <cr1901_modern> mithro: Consult on an hourly basis :)?

10:29 <whitequark> https://www.youtube.com/watch?v=UFqWjZudOho

10:50 <mithro> whitequark: HA! :P

12:16 <larsc> what?!

12:52 <GitHub41> [misoc] sbourdeauducq pushed 1 new commit to new: http://git.io/vnycD

12:52 <GitHub41> misoc/new f69674e Sebastien Bourdeauducq: interconnect: add bus/bank components from Migen

19:33 <cr1901_modern> whitequark: Did something "bad" happen to Rust? I remember you saying in your Foundry blog post that Rust keeps getting "better each day".

19:35 <whitequark> it does

19:35 <whitequark> it did then and it still does, I just don't really know if it's good enough

19:56 <cr1901_modern> What would have to change for it to be "good"? Isn't Rust meant to be a systems language? Unfortunately, it seems that runs contradictory to your goal of not using pointers at all.

19:57 <cr1901_modern> (Maybe a small library that implements flexible data structures like lists that doesn't depend on a runtime)?