<tnt> make sure your ground connect first and any potential difference between the two halves will go through that.
<pie__> tnt, also i think azonenberg_work was referring to the resistance of the diode and not the external resistor i was talking about?
<azonenberg_work> yes the diode resistance
<azonenberg_work> you are forming a resistive divider
<azonenberg_work> with the diode ESR to ground
<azonenberg_work> and the ESD source ESR to +lotsa voltas
<azonenberg_work> you want that voltage divider output to be below your gate breakdown voltage
<azonenberg_work> So the external resistor increases ESR of the ESD source
<pie__> sidenote http://www.vishaypg.com/docs/63129/esd_tn.pdf "Resistor Sensitivity to Electrostatic Discharge (ESD)"
<pie__> thin film resistors may not like esd? (not entirely surpisig?)
<pie__> im not sure if im reading figure 2 right, 1% change in resistance at ~ 3700V ?
<tnt> pie__: this is what I was proposing : https://sketch.io/render/sk-a20cf08113c05f5faf15957dee49ac3a.jpeg TVS will eat up most of the pulse. That's what they're designed for ... then the R + internal diodes of the device should be able to handle whatever clamped voltage the TVS diode left.
<pie__> tnt, yeah thats roughly where my minde ended up
<pie__> my question that was left was how to choose the resistor value
<tnt> Whatever suits the speed of your design ...
<pie__> thanks, ill read that
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<pie__> for positive swing voltage signals apparently unidirectional diodes are fine...so i guess i misunderstood something there *keeps reading*
<pie__> damnit i was typing up a summary to make sure i got things right and my irc client cleared it for some reason... :(
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<pie__> tl;dr: unidirectional esd diode normally works in reverse bias, the breakdown voltage specifies the overvoltage. it works in forward bias for negative esd voltage. a resistor in series with the data line can be used to limit the current
<pie__> the reason for working in reverse bias seems to be lower leakage current?
<pie__> given "voltage breakdown" specifies the protected voltage, im not sure what the point of a "reverse standoff" value is?
<pie__> or is it just removing the uncertainty in "operate at some value smaller than the breakdown voltage"
<pie__> couldnt you work at *any* value below the standoff voltage?
<sorear> you work in reverse bias because you don't want "normal voltages" to cause conduction
<sorear> modern inter-chip logic is 1-2V and silicon diodes will forward conduct at 0.7V
<pie__> sorear, ahhhhhh, for some reason i figured the forward voltage would be the same as the reverse, derp
<pie__> just because both protections protect you from ESD doesnt mean they have the same operating voltages, derp
<pie__> *both directions
<sorear> not clear if your application is using zeners or normal silicon diodes (~300V reverse breakdown)
<pie__> 300V sounds a bit much for 5v logic stuff :D
* pie__ is operating in low voltage regions
<sorear> sure, but if you're starting with a multi-kV ESD source it's a significant improvement
<pie__> sorear, i dont follow
<pie__> oh you mean 300v is still better than 30k? :p
<pie__> i did read something about two stage stuff but i doubt i need anything like that
<sorear> think of it like a mars landing. there is no one technology that (a) can survive a 10+ km/s entry (b) can get you to a <5 m/s terminal velocity
<pie__> hmm yeah orders of magnitude makes sense
<pie__> *orders of magnitude of operation
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<pie__> also it turns out its "clamping @ ipp" which means peak current. so thats the actual maximum voltage I think. so...it conducts at breakdown but can reach the clamping voltage...? that seems a bit weird but it makes sense on the diagram. so I guess I need to think about that.
<pie__> ok, thanks for all the help guys, i think i can finally make some sense of this
<_whitenotifier> [whitequark/Glasgow] whitequark pushed 3 commits to master [+3/-0/±3] https://git.io/fpoZq
<_whitenotifier> [whitequark/Glasgow] whitequark de0d5cf - gateware: add GatewareBuildError, for reporting constraint errors.
<_whitenotifier> [whitequark/Glasgow] whitequark eefae85 - gateware.pll: define interface.
<_whitenotifier> [whitequark/Glasgow] whitequark 38eac30 - gateware.platform.lattice: add PLL implementation.
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<_whitenotifier> [whitequark/Glasgow] whitequark pushed 1 commit to master [+1/-0/±1] https://git.io/fpoZr
<_whitenotifier> [whitequark/Glasgow] whitequark 1d14e23 - applet.vga_output: new applet.
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<pie__> tnt, I thikn I learned more from the an248 document you linked than most of the rest of the stuff I read
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<_whitenotifier> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpoce
<_whitenotifier> [whitequark/Glasgow] whitequark a4d2e56 - firmware: fix an operator precedence issue.
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<_whitenotifier> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpolf
<_whitenotifier> [whitequark/Glasgow] whitequark 65b3b2c - applet.vga_output: reorganize to support derived applets.
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<_whitenotifier> [whitequark/Glasgow] whitequark pushed 1 commit to master [+3/-0/±2] https://git.io/fpo0t
<_whitenotifier> [whitequark/Glasgow] whitequark c9af476 - applet.vga_terminal: new applet.
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<_whitenotifier> [whitequark/Glasgow] whitequark pushed 1 commit to master [+3/-0/±1] https://git.io/fpo0W
<_whitenotifier> [whitequark/Glasgow] whitequark 5121940 - applet.vga_terminal: add the rest of IBM VGA adapter fonts.
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<_whitenotifier> [Glasgow] kbeckmann opened pull request #87: applet.program_ice40: remove manual chunked writes - https://git.io/fpouw
<_whitenotifier> [Glasgow] whitequark commented on pull request #87: applet.program_ice40: remove manual chunked writes - https://git.io/fpour
<_whitenotifier> [Glasgow] kbeckmann commented on pull request #87: applet.program_ice40: remove manual chunked writes - https://git.io/fpoui
<_whitenotifier> [Glasgow] whitequark commented on pull request #87: applet.program_ice40: remove manual chunked writes - https://git.io/fpouX
<_whitenotifier> [Glasgow] whitequark commented on pull request #87: applet.program_ice40: remove manual chunked writes - https://git.io/fpouM
<_whitenotifier> [Glasgow] kbeckmann commented on pull request #87: applet.program_ice40: remove manual chunked writes - https://git.io/fpou9
<_whitenotifier> [Glasgow] kbeckmann closed pull request #87: applet.program_ice40: remove manual chunked writes - https://git.io/fpouw
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<_whitenotifier> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpogX
<_whitenotifier> [whitequark/Glasgow] whitequark d57dc12 - support.chunked_fifo: accept lists.
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<_whitenotifier> [whitequark/Glasgow] whitequark pushed 1 commit to master [+1/-0/±1] https://git.io/fpow3
<_whitenotifier> [whitequark/Glasgow] whitequark ee057bf - applet.vga_terminal: add boneless CPU and handle \r\n.
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<swetland> use "logic" everywhere appears to be hazardous... https://www.irccloud.com/pastebin/kyQYHpCt/
<q3k> swetland: yosys? vendor tools?
<q3k> now i'm curious what the standard says...
<swetland> verilator
<swetland> need to explore more widely
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<ZipCPU> I thought I looked into this recently
<ZipCPU> The issue is when assigning to a value at the same time you declare it
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<ZipCPU> It's not clear if its an assign A = B or an initial A = B statement
<ZipCPU> It could be either
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