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<awygle> TEMPERATURE constraint doesn't work on 7-series devices (or, indeed, 6-series)
<awygle> cool
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<sorear> Bob_Dole: atishp and maybe also davidlt have *some* AMD card working, idk exactly which one
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<SolraBizna> it wasn't the ground pin after all, it was !$#@ btrfs
<Bob_Dole> buttered filesystems sure are slick
<Bob_Dole> and prone to crashing into things
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<rqou> hey esden, did you actually want to borrow my T1 test set? i can bring it to supercon
<rqou> only real condition is that you need to return it eventually
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<Zorix> here i thought my workplace was the last one using T1s
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<whitequark> lol btrfs
<SolraBizna> woulda been using bcachefs, but after spending a whole week trying I couldn't run *any* custom kernel on this lump
<Bob_Dole> do rpis still need out of tree bits and bobs?
<SolraBizna> theoretically you can run one with a purely mainline kernel now
<SolraBizna> I say theoretically because I never even got serial console output
<SolraBizna> even if I got past that, I would never be entirely okay with the platform
<SolraBizna> all interaction between the ARM cores and the rest of the hardware is done with closed-source software running in an inaccessible context
<Bob_Dole> thought the videocore IV had full ISA released and had enough code to launch the arm core now?
<SolraBizna> there's an open source implementation that can boot the ARM cores, barely
<SolraBizna> but not, for instance, access USB
<Bob_Dole> USB is pretty important
<Bob_Dole> any access to the gpios? >.>
<Bob_Dole> I think there's another hat like that that uses HX parts
<sorear> in order to verify that the arm cores booted they would have had to have access to at least one piece of hardware
<sorear> .oO( debug console over physical covert channel )
<SolraBizna> the UART works
<sorear> aren't there rpi alternatives that are less cursed
<Bob_Dole> there's some that are more cursed
<SolraBizna> yeah, but I wasn't gifted one for free by someone who didn't know better
<SolraBizna> *one of the non-cursed alternatives
<Bob_Dole> is the Efika MX still a totally non-functional device in the modern era?
<Bob_Dole> because I got one still
<sorear> do you _want_ one? could you accept one without fucky financial effects?
<SolraBizna> I do and also don't
<Bob_Dole> wat
<SolraBizna> I accepted this R.Pi because I needed something to sit on the network, manage my backup array, be stable, and not consume gobs of electricity
<SolraBizna> not consuming gobs of electricity is the only thing it's been pretty successful at, and that's in exchange for consuming gobs of my time instead
<rvense> i've got one of those wandboards... been using it for mail and irc and other things for years
<SolraBizna> for things requiring lots of GPIOs and a bit of processing power (e.g. the 65test), I have an Arduino Due
<Bob_Dole> I've got 2 dues, and I think BOTH are knock-offs based off of early revision that had too weak of a resistor somewhere. I think manually resetting it was the usual fix?
<Bob_Dole> like, every time you wanted to use it, needs reset button pushed.
<Bob_Dole> I like that you actually know where to find a blog post about it. (I suspect it lists what resistor to replace too...)
<SolraBizna> the 65test is immune to that problem because it uses the reset-from-USB as part of normal functioning
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<SolraBizna> I would love to finish 65test, but that Arduino is currently acting as a really enormous, expensive UART-to-USB adapter
<Bob_Dole> should I mail you one of my spares and the 65c02?
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<SolraBizna> 65test is still all wired up, it's just that it's currently also connected via mangled fan connector to that R.Pi
<Bob_Dole> oh I thought your parents lost it for you.
<SolraBizna> they lost the KCCU and its Arduino
<SolraBizna> and my soldering station and my previous laptop and my mini desktop and ...
<SolraBizna> oh, and a whole bucket-bag of PCL
<Bob_Dole> that's expensive stuff :/
<SolraBizna> I managed to rescue my LC III + accessories and my G5 (though not the G5's funky power cable)
<Bob_Dole> funky power cable?
<SolraBizna> some of the G5s had a nonstandard connector on their power supply
<Bob_Dole> also does your LC3 still need re-capped?
<SolraBizna> we recapped it, it runs like a dream (as much as any LC III can)
<SolraBizna> that recapping project is the reason I know what hot tantalum dust smells like
<Bob_Dole> I bet you could make some classic mac expansion cards as a Product. >.>
<SolraBizna> I already made one, sort of... a serial-based external "hard disk"
<Bob_Dole> level shifters. fpga. SATA controller.
<Bob_Dole> and maybe modern ethernet.
<sorear> nubus to pcie
<Bob_Dole> I was just talking about that the other day
<Bob_Dole> specifically thinking of his lc3
<kc8apf> SolraBizna: those are still standard. Its a IEC C20
<SolraBizna> good to know
<SolraBizna> now that I think about it, I don't remember whether my G5 was one of those
<sorear> anyway if you're talking about things that cost a day's living expenses I could probably be convinced
<Bob_Dole> did macs ever have ramdisk expansion cards? I know Amigas did that, just stuffing a bunch of ram on a zorro card, and the OS would use it as slow-ram
* SolraBizna adds "butter up sorear" to to-do list
<SolraBizna> >_>
<Bob_Dole> buttering up your filesystem turned out poorly
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<SolraBizna> it only turns out poorly if I actually use it
<SolraBizna> see? that time I was able to type a command line without the SSH session timing out, this is fine
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<openfpga-github> [Glasgow] whitequark pushed 6 new commits to master: https://github.com/whitequark/Glasgow/compare/4c115e9317e0...d84a6a8baf28
<openfpga-github> Glasgow/master dca0b30 whitequark: firmware: simplify USB descriptor tables. NFC.
<openfpga-github> Glasgow/master 25d87d0 whitequark: firmware: update to newer libfx2....
<openfpga-github> Glasgow/master 9b86671 whitequark: firmware: remove now-unnecessary interrupt DPS hack.
<travis-ci> whitequark/Glasgow#124 (master - d84a6a8 : whitequark): The build has errored.
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<sorear> 1800-2012 and 1364-2005 do not make particularly clear how `define is supposed to be handled in edge cases
<sorear> is there a practical application for high-efficiency ecp5 bitstream compression (i.e. better than what can be done in hardware, but still decompressable with a small amount of C code)?
<sensille> sorear: if you have a small mcu on board that feeds the ecp5, it might even save an external flash
<sensille> i was thinking of building just that
<sensille> but how much better can you compress?
<daveshah> Might be interesting for folknology's BlackEdge board using an stm32 for programming
<daveshah> The USB 1.1 link will saturate before SPI
<sorear> how high does the stm32 clock?
<sorear> sensille: hard to say this early / without doing any research on the capabilities of the vendor compression
<sorear> sensille: for the purposes of this analysis let's say half size. dunno if that's remotely achievable
<sorear> actually hmm. does anyone have a reasonably large corpus of uncompressed bitstreams for various devices
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<felix_> balrog: the linux version of ise 14.7 works fine on windows 10 using the windows subsystem for linux. installed the debian variant, installed xorg in there and installed mobaxterm on the windows side and things just worked. well, i don't remember if it was ise where i had to patch the 32/64bit check out of the installationscript, but that was all i needed to patch for some of the xilinx software
<balrog> lol...
<Flux42> I tried that a while back. But ISE was just too painful to go back to.
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<openfpga-github> [Glasgow] whitequark pushed 3 new commits to master: https://github.com/whitequark/Glasgow/compare/d84a6a8baf28...1d91b91d4500
<openfpga-github> Glasgow/master 5ced761 whitequark: applet.program_ice40: parameterize over sys_clk_freq.
<openfpga-github> Glasgow/master 1d91b91 whitequark: applet.spi.master: parameterize over sys_clk_freq.
<openfpga-github> Glasgow/master 6035d76 whitequark: applet.hd44780: parameterize over sys_clk_freq.
<openfpga-github> [Glasgow] whitequark pushed 3 new commits to master: https://github.com/whitequark/Glasgow/compare/1d91b91d4500...b61a2f0d91ac
<openfpga-github> Glasgow/master 10e9c17 whitequark: applet.i2c.master: parameterize over sys_clk_freq.
<openfpga-github> Glasgow/master d094fb4 whitequark: applet.swd: parameterize over sys_clk_freq.
<openfpga-github> Glasgow/master b61a2f0 whitequark: applet.shugart_floppy: parameterize over sys_clk_freq.
<travis-ci> whitequark/Glasgow#126 (master - b61a2f0 : whitequark): The build has errored.
<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/755bf65c322766d0bdfec1510300792d7e539901
<openfpga-github> Glasgow/master 755bf65 whitequark: applet.rgb_grabber: parameterize over sys_clk_freq.
<openfpga-github> [Glasgow] whitequark commented on issue #71: Done. https://github.com/whitequark/Glasgow/issues/71#issuecomment-435073262
<travis-ci> whitequark/Glasgow#127 (master - 755bf65 : whitequark): The build has errored.
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<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/1e72aa4389defcf0561962526ce2e4b9f2ce0506
<openfpga-github> Glasgow/master 1e72aa4 whitequark: Untangle USB pipes from I/O ports....
<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/27e470feeea5422ee606aad3313a71518c88ffed
<openfpga-github> Glasgow/master 27e470f whitequark: applet.shugart_floppy: formatting. NFC.
<travis-ci> whitequark/Glasgow#129 (master - 27e470f : whitequark): The build has errored.
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<kristianpaul> o/
<kristianpaul> o/
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<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/703e4c47c2976e3a527aed43b6771a4b704d5248
<openfpga-github> Glasgow/master 703e4c4 whitequark: applet.jtag: implement (very danger/u/s) enumerate-ir operation.
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<sorear> so trying to get a feeling for what the useful frontier of compression ratio vs. cpu time is
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<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/4569b3f5195bd16f7133ed19c1b4f892c61305cf
<openfpga-github> Glasgow/master 4569b3f whitequark: applet.jtag: unbreak enumerate-ir operation, handle DR[0] case.
<Bob_Dole> how do ECP3s compare to ECP5s, and are they at all similar under-the-hood?
<travis-ci> whitequark/Glasgow#131 (master - 4569b3f : whitequark): The build has errored.
* Bob_Dole noticed they're bigger and a lot more expensive
<sorear> the ECP3 and the ECP5 are iterations in the same niche
<sorear> the ECP5 is faster and cheaper at a given size, the largest ECP3 doesn't seem to have an ECP5 counterpart yet
<openfpga-github> Glasgow/master e20ad9a whitequark: applet.jtag: fix incorrect doc.
<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/e20ad9aebcc53beb210bc1137a087ad6c17d4652
<Bob_Dole> I was wondering if it was a differentiation in application, if they were perhaps not power-efficient but fast(er) while bigger. Is there any indication Lattice might put out some bigger ECP5s?
<gruetzkopf> i'd love a ECP5 with more SERDES blocks
<travis-ci> whitequark/Glasgow#132 (master - e20ad9a : whitequark): The build has errored.
<gruetzkopf> like, double what's available would be a good start
<daveshah> Ecp3 tools are probably doable, but the effort would be better spent on 7 series imo
<sorear> Given that ECP3 is listed under http://www.latticesemi.com/en/Support/MatureAndDiscontinuedDevices
<Bob_Dole> Oh. I was looking on Mouser, only a couple ecp3's seemed to have NRND status. (and was asking if they were similar under the hood for if adding support would end up being Easy.)
<Bob_Dole> I was thinking of, I think one of the MAX cplds had an older variant using the same bitstream format?
<sorear> yes
<sorear> MAX II versus MAX V i think? rqou's bailiwick
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<sorear> can probably reuse most of trellis to do ecp3 if you wanted to
<sorear> my priorities are generally based on "how likely is someone to need this", which for a NRND chip is probably just s6 and similar due to the sheer number of s6 devboards random people have
<Bob_Dole> yeah, I didn't realize they were all NRND because of mouser only labeling a few as it.
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<daveshah> Yes, most of the bitstream parser and fuzzers could be reused. But you'd have to rerun the fuzzers and modify tile names as needed, etc
<daveshah> But as I say 7 series is probably a better use of time than ecp3
<daveshah> the main advantage of ECP5 over 7 series is cost
<daveshah> Which the ecp3 doesn't really have
<sorear> unclear how compelling the intel and microchip lines are
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<daveshah> Larger intel parts might be trouble because of the redundancy stuff and the stories about silicon bugs being worked around in their software. Don't know how true that is
<daveshah> Microsemi is more interesting imo
<daveshah> With their non volatile and low power stuff
<daveshah> Also the cortex m3 SoCs
<sorear> the microsemi stuff is true nonvolatile, which could be useful for some stuff (900 µs from POR to output drivers active according to the polarfire DS)
<Bob_Dole> prior to learning what I have, I hoped they'd end up being faster, like older ice40s are faster than the new UPs, and they'd be a relatively-simple thing to add until 7 series can be done, as a stop-gap... but slower and more expensive. blah.
<sorear> still surprisingly high, and might be in a tight race with the more optimized CPLDs
<sorear> well this is more like comparing an ice40 to an ice65
<daveshah> I do wonder if Lattice's next parts will have a hard RISC V core
<daveshah> As they have joined RISC-V
<sorear> I don't even have downloaded any Intel/Altera datasheets, they must be useful for something though
<daveshah> Hard floating point is quite cool imo
<sorear> does microsemi have designer programmable hard M3s on any parts?
<Bob_Dole> I know Altera's Cyclones used to be popular around the time of Xilinx's 3 series Spartans being everywhere
<Bob_Dole> and then they dropped off the map at some point and until the foss toolchain I was only seeing xilinx used for anything at all
<Bob_Dole> excluding intel talking about putting them on cpus
<rqou> cyclone arch is nice if you're obsessed with micro-optimizations
<daveshah> sorear: SmartFusion
<rqou> altera product naming is kinda a disaster though
<rqou> as are family trees
<Bob_Dole> the first time I heard anyone using altera again.. was that surprise move by arduino, using the intel parts, not just with a proprietary toolchain, but cloud-based proprietary.
<daveshah> With things like the Cyclone 10 LP, Cyclone IV E and Cyclone III all sharing the same IDCODE iirc
<rqou> yeah, they're allegedly bitstream compatible too
<rqou> meanwhile cyclone 10 gx is a completely different arch
<daveshah> Not timing compatible though
<daveshah> At least III and IV E are different processes
<Bob_Dole> I was kinda interested in the Intel stuff for a bit because of the OpenCL integration in their toolchains. Interested because of mining and the first discussion of FPGA-offloading of algo parts being able to make such a big improvement
<rqou> oh yeah, timing is different
<rqou> max ii/v are also bitstream compatible
<Bob_Dole> speaking of the max ii/v, what state is the toolchain in for them, and.. what reasons might they be considered over the ice40s, for instance? >.>
<daveshah> Non volatile is probably a big advantage
<Bob_Dole> is it not OTP so can be reprogrammed later? because oh yes
<Bob_Dole> that would be a huge advantage
<daveshah> It's flash I believe unlike the ice40
<Bob_Dole> if the toolchain is working, then SolraBizna may find some interest in that
<sorear> my understanding is that MAX uses a flash separate from the SRAM config, but they're connected by a very wide bus so the load takes a few 100 cycles
<daveshah> Yes, similar to MachXO I think
<daveshah> Whereas ice40 NVCM loads at SPI type speeds
<sorear> contrast ice40, where configuration from NVCM is bit-serial exactly as external config, and polarfire etc which don't have config SRAM (the flash transistors drive the control signals directly)
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<awygle> polarfire is flash-based too? i didn't know that
<awygle> that's cool
<awygle> 10gx is supposed to be... i think arria v? it's not a new arch, although it's different than 10lp
<awygle> at least that's my understanding
<awygle> and i too would like an ecp5 with twice the serdes and maybe 50% more logic for various reasons
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<prpplague> tinyfpga: great writeup on the new pcbs
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<prpplague> tinyfpga: (i'm Dave's Dev Lab on hackaday)
<prpplague> azonenberg_work: softiron is who i work for
<prpplague> azonenberg_work: we actually have "chain of custody" for parts
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<azonenberg_work> prpplague: verified how? say you have a xilinx fpga that was fabbed at tsmc, the wafer went to a wirebonding factory on the other side of taiwan
<azonenberg_work> chinese intelligence comes in and intercepts the package, does a few fib cuts on the wafer, then forwards it
<azonenberg_work> can you detect that?
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<marshallh> wouldn't they be working at TSMC already
<prpplague> azonenberg_work: yea, i can't got into details, but it was more to point out that we work and target specific customers who have "concerns" about the types of hardware attacks we have discussed
<azonenberg_work> marshallh: that too, i was just pointing out an example
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