<sorear>
what kinds of cheap chips would have DDR3 or DDR4 interfaces better than 800 MT/s
<prpplague>
sorear: few "cheap" chips
<prpplague>
sorear: if any
<prpplague>
sorear: i can;t think of single one that you can get your hands on
<sorear>
like a $5ish ecp5 can do 800 MT/s * x16 = 1.6 GB/s to a $5ish DDR3 chip; on the memory side you can definitely go much faster without a significant increase in cost but finding suitable controllers could be a challenge
<azonenberg_work>
sorear: artix7 -3 can do ddr3 1066
<azonenberg_work>
kintex7 -1 can do ddr3 1600 if you bump vccaux_io up to 2V, with default 1.8 it can do 1066
<azonenberg_work>
in -2 you can do 1866 at 2.0V and 1333 at 1.8
<Bob_Dole>
dem speedgrades
<Bob_Dole>
how Wide could you reasonably go on ecp5 if you want to take that route over fast?
<Bob_Dole>
I haven't looked at their packages to get pin count or speed capabilities of them
<azonenberg_work>
Bob_Dole: i wouldnt go much over 32 bits on a dram controller, maaaybe 64
<azonenberg_work>
per channel
<azonenberg_work>
routing would be a nightmare after that
<Bob_Dole>
it's a thing that might come up in the next year though, after SolraBizna's FACT has been made.
<azonenberg_work>
FACT? is that that monster ecp5 cluster?
<Bob_Dole>
FACT is just Durable 16bit computer with Some expandability.
<Bob_Dole>
with a 65816 and ice40, an mram, and some sram at base level stuff.
<Bob_Dole>
not sure I'll be commissioning him to do the GPU portion of desired risc-v system, or the risc-v system. Doing GPU probably has benefits in having an ecp5 and ram on a board that can be used for other development after getting the core and some driver work done on a normal desktop environment
<Bob_Dole>
but that still.. is like 2 projects out. (ohgodastoldertest and fact.)
<Bob_Dole>
thoughts moved to ust have an ecp5, http://www.ti.com/product/TFP410, and I WAS proposing a wide pseudo-sram thing for the sake of simplicity, but if ddr3 is achievable why not? and a pci(e) interface.
<Bob_Dole>
slightly tweaked risc-v core and tweaked llvmpipe to complement it as the Core/Driver
<sorear>
$needsaname, operated as a vector machine, would have relatively terrible FP perf but actually competitive memory bandwidth :p
<sorear>
i'm a little unclear how llvmpipe works in an asymmetric multiprocessing situation
<sorear>
if I have N cores but only one of them is wired for vector issue
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<Bob_Dole>
being able to pair multiple cores in NUMA for llvmpipe to be able to use multiple fpgas to expand performance would be nice.
<Bob_Dole>
but I am, at this very moment, considering "can I actually get solra to design this board and hack together a driver for it at all"
<bubble_buster>
anybody familiar with bluespec? seems to be abandoned or in stealth mode?
<Bob_Dole>
MIAOW might be a better thing to start from but there's risks in potentially pissing off amd. >.>
<Bob_Dole>
I'm not, but now I want to know what that is, bubble_buster
<sorear>
if you're not Threatening Their Revenue you don't have much to worry about
<sorear>
bluespec is a company with a commercial-only HDL
<bubble_buster>
seems to be heavily haskell based/inspired
<Bob_Dole>
except companies sometimes feel obligated to sue, to make sure they can sue anyone that has a chance of threatening their revenue
<Bob_Dole>
avoid the xerox situation and all that
<sorear>
they're not dead, they're releasing new stuff just a few days ago
<sorear>
it's hard for me to get too excited about a language with a proprietary compiler
<Bob_Dole>
I am actively researching topics to develop a computer that would probably be roughly equivalent to my 400mhz Sun Ultra 5, to avoid proprietary.
<sorear>
on the other hand, they're a (long) walk from here, and I'd like to meet the people involved *somehow*
<SolraBizna>
does a HiFive Unleashed count as proprietary?
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<Bob_Dole>
no, but it counts as probably costing more than a couple fpgas with pci(e) linking them and maybe 100 dollars of RAM on it.
<Bob_Dole>
and still probably needing the gpu side of things.
<Bob_Dole>
and the gpu side of things maybe useful for getting useful graphics on a sun ultra 5 at this point in time.
<SolraBizna>
I wouldn't be able to make a GPU that's faster than a FU540 running llvmpipe
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<Bob_Dole>
but how much of the fu540 be taken up running llvmpipe
<Bob_Dole>
and also I was thinking about the U5 earlier. really sucks that All of its available GPUs have had driver dropped.
<Bob_Dole>
and onboard only does 800x600 anyways.
<sorear>
i'd like to see statistics on exactly what MATE (fex) needs the GPU to do
<Bob_Dole>
useful info, I'm sure.
<Bob_Dole>
(especially for desired application here.)
<sorear>
the FU540… about 1/3 of the silicon area is for the four independent fma.d
<sorear>
cores
<sorear>
your gpu probably doesn't need 12 double precision GFLOPS
<sorear>
(although that's kinda low by GPU standards, it's quite out of proportion with what the rest of the chip can do)
<Bob_Dole>
the things I don't like about the FU540 is.. it uses a xilinx fpga to get an expansion bus on it and it costs 1k for a single board, without that.
<sorear>
right, doing anything with shuttle chips is problematic
<sorear>
hoping somebody mass-produces something with an exposed memory bus
<Bob_Dole>
the FE310 would be nice if it had an exposed memory bus
<SolraBizna>
the 65816 has all the processing power anyone could ever need
<Bob_Dole>
get it running MATE and iceweasel
<SolraBizna>
it was really hard to say that with a straight face
<sorear>
dunno, factoring 512-bit numbers on the 65816 will be a slog
<SolraBizna>
just need enough of them
<sorear>
nobody needs to run iceweasel, but
<Bob_Dole>
it might be a little harder to get chromium going
<SolraBizna>
in seriousness, I don't know of any semi-modern web browser that can run in 16MiB of memory space
<Bob_Dole>
yeah. Opera's Presto is the last thing I know of that was doing it
<Bob_Dole>
and presto is dead
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<SolraBizna>
sometimes I toy with the idea of making a giant computronium cube out of 65816es
<Bob_Dole>
fpgas make it possible
<SolraBizna>
it would be more fun if the gap between a 65816 and a "real CPU" weren't so great
<cr1901_modern>
The only truly massive proble is the addr space.
<cr1901_modern>
I just want an https/ssh impl on 6502/65816 and I would be happy, tbh. I can work around everything else.
<cr1901_modern>
problem*
<SolraBizna>
Doesn't sound too h...
* SolraBizna
suddenly remembers that the S in HTTPS is for SSL
<cr1901_modern>
Well, it's what the entire internet uses. And not much fun w/ homebrew that can't connect to other machines :)
<cr1901_modern>
Deferring TLS stuff to an accelerator isn't a problem if it's truly impossible for 6502 to do TLS under its own power, but "using a computer orders of magnitude more powerful" defeats the point of retrofitting IMO
<SolraBizna>
It's very possible, if you don't mind it being slow
<Bob_Dole>
aren't there timeouts on that stuff
<Bob_Dole>
so being slow can make it impossible
<cr1901_modern>
That's what I'm afraid of
<cr1901_modern>
I want possible, not fast
<SolraBizna>
Hm...
<Bob_Dole>
math time?
<cr1901_modern>
sorear: ^^ Didn't you do the math?
<sorear>
yes
<sorear>
a 6502 can do a multiplication mod 2^255-19 in ~ 30K cycles
<sorear>
at 1MHz, a curve25519 montgomery ladder takes about 2 minutes
<sorear>
if you have 2MHz it should be very doable
<Bob_Dole>
the 65816 mcu we're looking at can do 6-12mhz I think
<Bob_Dole>
depending on voltage
<cr1901_modern>
wdc silicon goes up to 14mhz officially; ppl have done up to 20mhz
<cr1901_modern>
for 65816 and 25mhz for the 6502 impl they have
<Bob_Dole>
14mhz is at 5v though
<Bob_Dole>
can't use very many memories with that anymore
<cr1901_modern>
yes, in my case I would be using that :)
<cr1901_modern>
Then I'll use dual voltage level shifters
<Bob_Dole>
(bolt I suppose fast level shifters do exist)
<cr1901_modern>
it's not worth losing half the bandwidth for that
<Bob_Dole>
bolt? though*
<Bob_Dole>
how the hell did I typo though as bolt
<sorear>
Bob_Dole: bi-directional level shifters are very cursed
<cr1901_modern>
I wouldn't use a bidir level shifter
<Bob_Dole>
sorear, I've been a little worried about that detail
<whitequark>
!track SCSI
<whitequark>
glasgow scsi applet, how cursed is that
<cr1901_modern>
wrong room?
<whitequark>
oh
<whitequark>
oops lol
<whitequark>
seriously though
<whitequark>
does anyone want it
<Bob_Dole>
I haven't seen much about bi-directional level shifters that are usefully fast
<cr1901_modern>
sorear: Err, autosensing bidir level shifters I wouldn't use
<whitequark>
Bob_Dole: fxmas are up to 50 MHz
<cr1901_modern>
ones with a manual dir pin should be fine
<whitequark>
SN74LVTCs are like 250 MHz
<sorear>
and the output will glitch at 50 MHz no matter what freq the input is!
<whitequark>
yes
<Bob_Dole>
I think I was looking at something adafruit was using that were way too slow and that's the only application I actually saw of them in use.. I suppose until whitequark's glasgow but I know nothing about those still. >.>
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<cr1901_modern>
SCSI has really stupid complex termination and cables :/ (well the 68 pin version anyway)
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<Bob_Dole>
I keep seeing that futaris nick.. brain is autocompleting it to something different.
<whitequark>
same >_>
<whitequark>
also: futarchy
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<cr1901_modern>
whitequark: How do you think I feel? We have a FUTA tax here.
<whitequark>
incredible
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<mwk>
hey guys
<mwk>
if anyone still has one of those laying around, I made a simple hacky script to program the FPGA on Digilent Basys 2 boards without using vendor tools
<mwk>
I'm also going to add support for host-FPGA communication through the EPP protocol soon
<mwk>
and: it seems a lot of other Digilent boards are using the same or same-ish protocol, so if anyone has such a board, I'd very much appreciate usbmon pcaps of you programming the FPGA via vendor tools
<mwk>
especially if the device identifies as 0x1443:0x0007
<mwk>
(but it seems there are likely other IDs that could be similiar)
<azonenberg_work>
Nice, i'd love to add jtaghal support for those pogrmamers but dont have the time
<azonenberg_work>
(pull requests welcome though)
<azonenberg_work>
i can test on an Atlys once i dig mine up
<azonenberg_work>
all of the boards i have handy right now are ftdi based
<mwk>
are they digilent though?
<azonenberg_work>
the atlys is
<mwk>
there are some signs they could still use the same-ish protocol, just over a different transport
<azonenberg_work>
the ac701 is a xilinx board with a digilent programmer module, ftdi based though
<azonenberg_work>
the atlys has a... cypress mcu of some sort?
<mwk>
fx2?
<mwk>
yeah, those too
<azonenberg_work>
i suspect
<azonenberg_work>
but i havent looked at it in a while, it lived on a rack inside an old sun netra case :p
<mwk>
AFAICT they use the same protocol, but you have to upload some fw to them to get them to speak it first
<mwk>
while the basys2 has a preprogrammed AVR on it
<azonenberg_work>
ah ok
<azonenberg_work>
actually wait
<azonenberg_work>
no it wasnt a fx2
<azonenberg_work>
it was a pic
<azonenberg_work>
pic24 or pic32
<mwk>
hm
<mwk>
*shrug*
<azonenberg_work>
or was that for the usb-ps2 interface?
<azonenberg_work>
i cant remember
<azonenberg_work>
i'll check when i get a chance
<mwk>
I'd say usbmon it and see :)
<mwk>
anyway
<mwk>
my main motivation for this is getting the EPP communication working
<azonenberg_work>
more like, figure out which box it lives in :p
<mwk>
for a uni project
<azonenberg_work>
i have stuff all over the place during the construction
<mwk>
programming it through jtag is just a bonus
<azonenberg_work>
the only thing i have handy right now is my ac701
<azonenberg_work>
and i had to move quite a few boxes to find it
<mwk>
I quite like the lcient-server model of jtaghal
<mwk>
but I suppose I cannot use it for anything other than jtag, right?
<azonenberg_work>
It has very early stage SWD support
<azonenberg_work>
and i do plan to eventually add other programming algorithms like PIC ICSP
<mwk>
yeah, but
<mwk>
I don't want to use it for programming
<mwk>
but to talk to the already-programmed FPGA
<azonenberg_work>
i have support for GPIO through FTDI programmers already
<azonenberg_work>
adding more complex gpio functionality is totally doable
<azonenberg_work>
i've also implemented my own antikernel noc over jtag protocol using it
<mwk>
so ideally I'd like to have some hardware manager that handles the different ports of the USB device
<mwk>
and connect EPP communication / JTAG programming to it through independent sockets
<mwk>
EPP is not GPIO though, they handle it in the AVR firmware
<mwk>
you send address, data tuples and it hanldes the protocol for you
<azonenberg_work>
doesnt matter, from the perspective of a jtaghal client
<azonenberg_work>
it's some kind of additional io interface on the programmer
<azonenberg_work>
you might be able to bolt it on by exposing it as a debugger interface
<azonenberg_work>
treat it as a memory mapped device
<azonenberg_work>
not sure yet
<azonenberg_work>
if you implement the programmer protocol we can talk over the best way to fit in the other features
<keesj>
mwk: nice (to have a python based programmer)
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