<pixelherodev>
I think the biggest section is astgen right now
<pixelherodev>
That's what needs the most work, rather
<pixelherodev>
astgen is basically what "understands" Zig code (in the form of the AST), and translates to the IR
<pixelherodev>
so it goes from e.g. `if (a) {b }` to `condbr(a, { b })` - which codegen sees and turns into e.g. z80's `jz`
<pixelherodev>
Relatedly, a lot of work is needed on codegen
<pixelherodev>
For x64 work - which is most crucial, since most zig development occurs on x64 - codegen isn't *complete*, but there's enough of it to support a good chunk of astgen without needing codegen work
<qeeg_>
yeah i'm on x64 :p
<pixelherodev>
I'm not sure anyone would outright *reject* optimization work, but it would have to come with the understanding that changes in the compiler might require constant work to keep it up to date - which nobody wants, so nobody really cares to work on it yet
<pixelherodev>
We also, for the record, have *no* intent of *ever* matching GCC / LLVM level of optimizations
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<qeeg_>
uh why not? o.o
<pixelherodev>
Because, to put it frankly, their optimizations are ludicrously complex and not worth competing with
<pixelherodev>
We don't *need* to match their performance
<pixelherodev>
Basic optimizations will get us a very large percentage of the way there
<pixelherodev>
If maximum performance is the goal, LLVM (or possibly GCC) will be needde
<pixelherodev>
needed*
<qeeg_>
well, is there any way i could learn about basic optimization stuff for compilers?
<pixelherodev>
I think the best optimizations Zig can develop internally would be architectural ones
<pixelherodev>
Tweaking codegen based on microarchitecture, effectively
<pixelherodev>
`-march=native` on GCC / Clang does this
<pixelherodev>
Basically, some instructions have different performance characteristics on different *micro*architectures
<pixelherodev>
e.g. Ryzen vs Skylake vs Bulldozer vs Kaby Lake etc
<pixelherodev>
GCC takes it a step too far IIRC, but the general idea is sound
<pixelherodev>
The general optimizations I'd love to see in Zig are microarchitectural, inlining, dead code elimination (DCE), common subexpression elimination (CSE), and constant folding
<pixelherodev>
That alone should at least make for good debug builds produced rapidly
<pixelherodev>
Optimizing a dynarec is much easier when there's few interacting parts
<ifreund>
they even seem to have a fairly normal coding style
<pixelherodev>
With one minor problem
<pixelherodev>
That linked list definition is gross
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<pixelherodev>
and.. they seem to use a linked list where one really isn't needed...
<pixelherodev>
I think a dynamic array would've worked better in the random file I just opened and have no context for
<pixelherodev>
:P
<ifreund>
heh
<pixelherodev>
anywho, I'm going to get to work for realsies, I don't think "I was playing with an emulator's source" is a valid excuse for, well, anything
<ifreund>
both data structures kinda suck in C due to lack of typesafety or overabundance of macros
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<qeeg_>
ifreund, yeah, it's just that weirdly, you start to get diminishing returns with the emulator's speed, with faster host cpus
<qeeg_>
which doesn't make much sense to me?
<qeeg_>
like, even though the emulator doesn't even use the gpu much at all (literally just to blit a framebuffer to the screen), faster cpus don't really do much for it
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<pixelherodev>
qeeg_: is it threaded?
<qeeg_>
partially
<pixelherodev>
Single thread performance hasn't been increasing all that quickly for the last... decade or so?
<pixelherodev>
At least
<pixelherodev>
my eight year old CPU has ~70% the single-thread perf of a modern Ryzen 7 IIRC
<qeeg_>
the cpu emulation happens on one thread, but a lot of other stuff is offloaded to other threads
<pixelherodev>
If CPU emulation is the bottleneck, that might explain it
<pixelherodev>
It's also possible that there's a lot of threading contention
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<pixelherodev>
qeeg_: if you have any questions, feel free to ping me here
<qeeg_>
aight, thanks
<pixelherodev>
I might not always be able to respond instantly, but I have a good deal of experience with the Zig stage2 compiler and am glad to help out :)
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<pixelherodev>
I think I might legitimately be able to cross 1GHz without issues
<ikskuh>
:D
<ikskuh>
z80 → x86 is a good jittable arch :D
<ikskuh>
"just copy over the bytes and patch some" :D
<pixelherodev>
I'm not doing direct to x86
<pixelherodev>
This goes through RISC-V first ;)
<pixelherodev>
also yes I *am* abusing my graphics library by pretending the CPU is a custom widget and having it be executed by the window rendering code :P
<pixelherodev>
ahhh whoops
<pixelherodev>
I'm using the TI ASIC MMU, which is slowing everything down massively
<pixelherodev>
What I really need to do is JIT away the MMU access :)
<pixelherodev>
Could probably cache opcode lookups until pages are swapped
<pixelherodev>
Woot! 1GHz on the laptop!
<pixelherodev>
1.24GHz, even
<pixelherodev>
and shockingly these optimizations are actually useful :P
<pixelherodev>
ikskuh: I think I can make this specific microbenchmark even more insane
<pixelherodev>
I figured out how to hit THz levels
<pixelherodev>
When translating some address X, and a nop is encountered, trawl from X until either the end of the address space or a non-nop value is encountered
<pixelherodev>
Produce a function which simply adjusts `cycles` and `cpu->registers.PC`
<pixelherodev>
That'll process 64K NOPs in the time I can currently process one :P
<pixelherodev>
So, 128THz on my PC
<pixelherodev>
Why am I like this
<pixelherodev>
ikskuh: "my SPU II emulator is over a million times faster than yours!!!"
<pixelherodev>
actually, due to the 16-bit instructions on SPU II, it'd be a tad slower
<pixelherodev>
Still THz insanity though
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<Michcioperz>
our scientists were so preoccupied with whether or not they could
<pixelherodev>
Still, anything that can emulate 262144 cycles in the space of two x86 `mov`s is obviously stupid, even if this is fun to make
<pixelherodev>
Michcioperz: lol
<pixelherodev>
On a modern microarchitecture, I think this could hit... *technically*... about two hundred thousand instructions per (physical) cycle?
<pixelherodev>
It could tear through the full address space probably *twice* in a single cycle lol
<pixelherodev>
The thing is, this wouldn't slow down real uses
<pixelherodev>
So there might not be a practical benefit, but the entertainment is free :)
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<ifreund>
so std.os.toPosixPath() returns a pointer to a stack variable
<ifreund>
how is this safe? is this guarenteed to be safe if no other function is called before the variable is used?
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<ifreund>
wait no I can't read
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<ask6155>
hello
<ifreund>
o7
<ask6155>
my master zig compilation was failing. I deleted the build folder and tried again I was building but at the last stage it hanged my pc. The last one was 99% building self-hosted component /home/user/zig/zig1.o It ate all my ram and started eating my swap. I killed it. I then turned my swap off and tried. It failed at the last step with an allocation failure. I was able to build it before and I have 4GB ram.
<ask6155>
Also I noticed it certainly does have a kind of poetry to it. If you know what I mean
<ifreund>
ask6155: The quick fix would be using a commit from before #6250 was merged
<ask6155>
what was it?
<ifreund>
this PR moved a LOT of C++ to Zig code and increased the size of the zig1 codebase significantly
<ifreund>
unfortuneatly the C++ zig0 compiler is not at all memory efficient, so it sounds like this change was enough to push things over the edge for your machine
<ask6155>
so you mean I can't compile it?
<ifreund>
there are some ideas to make the zig0 compiler more efficient as a stopgap until the self-hosted compiler is feature complete
<ifreund>
(the self hosted compiler is WAY more memory efficient and faster than the stage0 C++ implementation)
<ask6155>
One of the things I like about zig was I could actually compile the compiler and use it unlike all the other compilers. I wouldn't want to loose that
<ifreund>
feel free to open an issue to discuss, I agree that this is a problem
<ask6155>
can you tell me the commit hash at which this was changed?
<ikskuh>
ask6155: 0.6.0+f8b3543ca is still using the old system
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<ask6155>
I created an issue
<ask6155>
building the compiler is a thing noone really cares about. The only other compiler I can think of that I can compile is tinycc.
<ikskuh>
i really love how easy building Zig with cmake is
<ask6155>
is it safe running gdb with sudo?
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<ifreund>
afaik yes
<ifreund>
you need privlages for some of gdb's functions in fact
<ask6155>
ok I was asking because gdb was using ptrace and I had set it so that ptrace can only be used by privileged users
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<fgenesis>
uhm apparently there's a nullptr dereference somewhere in the zig part of the zig compiler. tried to compile a .c file on a rpi4 and after adding an asm volatili("yield") in the .c file it kept segfaulting
<fgenesis>
plus valgrind finds a bunch of "conditional mode depends on uninitialized value"
<fgenesis>
was testing the arm7 binary release of zig 0.6 yesterday
<fgenesis>
didn't bother to debug it but likely will sometime this weekend if anyone is interested
<ikskuh>
fgenesis: not really relevant atm. some days ago, #6250 landed and rewrite 20kLOC of the stage1 compiler
<ikskuh>
*rewrote
<fgenesis>
*conditional move
<fgenesis>
thought as much
<fgenesis>
still wanted to mention it for completeness
<fgenesis>
i'll probably go and build zig master when i have the energy for it
<fgenesis>
oh and i wanted to mention that the biitstrap build script is broken for me, i'm apparently too dumb to supply the right cmdline args to make it past line 13
<fgenesis>
*bootstrap (gah i can't type today)
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<fgenesis>
compiling llvm10 on a pi4 takes a long time indeed
<fgenesis>
don't even want to know how a pi1 or 2 would cope *brr*
<fengb>
Pi1 falls over due to memory
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<fgenesis>
not if you enable swap
<fgenesis>
and plan in extra time
<ikskuh>
wear out that SD-Card!
<ikskuh>
or even better: use a file on NFS for swap!
<fgenesis>
nah, just put the swap on a usb-hdd
<fengb>
I mean... swapping out that 512 MB is doable
<fengb>
But that's akin to falling over to me
<fgenesis>
or remote-smb-share backed by a ramdisk. remote-ram as a service
<fengb>
Hmm... is there a way to make the VRAM config more fluid? Rebooting each change is annoying
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<nikki93>
shachaf: nice :o i was using entr for it http://eradman.com/entrproject/ which works on macos and happens to work on windows wsl too
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<ikskuh>
hm
<ikskuh>
anyone an idea why zig emits a call to __memcpy_chk when building for x86_64-windows-gnu?
<ikskuh>
and where this might come form
<ikskuh>
aha!
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<ikskuh>
zig sneakily sets _FORTIFY_SOURCE
<donniewest>
Has anyone considered setting up a bridge between zig's Matrix and IRC services? It'd make following all the conversations easier :)
<donniewest>
Neovim has, uh, all the services (Gitter, Matrix, IRC) and they all bridge together so anyone can join the conversation anywhere. Makes things pretty nice
<tdeo>
neovim? :)
<ikskuh>
donniewest: zig community is decentralized. i have no idea how much chats are going on :D
<tdeo>
though i think a bunch of people join this irc from the matrix bridge
<Nypsie[m]>
donniewest: There's already a bridge between Zig's Matrix and IRC
<tdeo>
ignore my first message, misread that one
<Nypsie[m]>
In fact, I'm sending this message through the Matrix bridge as we speak :)
<donniewest>
That's weird. I'm on the Matrix room and I don't see these same messages?
<fgenesis>
... which means only irc is needed. end of discussion :D
<donniewest>
I know Matrix can connect to Freenode, but it's still ultimately separate rooms. I personally prefer IRC, so a bridge to let me see those messages would be great
<Nypsie[m]>
Ooooh, you mean like that. That's currently not done, no
<earnestly>
That would be done with a bot, essentially. It's not fun "talking" to bots on IRC because, at least, it breaks nick display
<donniewest>
Well, if there's interest, I'd be happy to lend a hand :)
<donniewest>
Yeah, the nick sync is a bit weird. Neovim's seems to handle it alright but there's still a bit of a disconnect
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<nikki93>
https://imgur.com/a/39spS3N beginnings of immedate mode dom ui api -- mostly planning on using it to edit properties for the scene i render with webgl
<Nypsie[m]>
Cool!
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<pixelherodev>
Heads up to the ziglibsers that I left the GitHub org; I just deleted all my repos except for the zig branch (which is staying until PRs are merged)
<pixelherodev>
wootehfoot, alexnask[m]: I didn't delete any organization repos.
<pixelherodev>
I delted repos under github.com/pixelherodev/*
<pixelherodev>
and I *left the org*
<pixelherodev>
deleterd*
<alexnask[m]>
ah, okay, mb
<pixelherodev>
deleted*
<pixelherodev>
Two different things
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<pixelherodev>
alexnask[m]: no worries :)
<torque>
<donniewest> I know Matrix can connect to Freenode, but it's still ultimately separate rooms. I personally prefer IRC, so a bridge to let me see those messages would be great <-- I personally disagree with using bridges between different services
<torque>
drops the signal to noise ratio like a rock
<nikki93>
quick q: how do i convert an integer to a float to multiply by a float? eg. if i have an integer 10, then want to multiply by 0.1 and get 1.0
<alexnask[m]>
@intToFloat
<nikki93>
i see
<nikki93>
thx!
<shachaf>
nikki93: Oh, if you're using Windows then I don't know if it'll work, since it uses ptrace.
<nikki93>
i'm mostly on linux or mac but i use windows too :)
<nikki93>
the inline styles are mostly for quick testing, mostly planning on just setting css classes in code and keeping the styles in css files elsewhere
<pixelherodev>
whatcha working on?
<nikki93>
just exploring what using zig looks like for web graphics and ui stuff
<nikki93>
especially ui for editing those graphics
<nikki93>
so that you could do a level editor for a game etc.
<nikki93>
the main thing i'm curious about when i get there is abt using zig's reflection and comptime stuff to generate ui for the structs of data
<cr1901_modern>
I asked this before, but I'll ask a different way... if I'm using a zig package (regex) that's known to leak memory, what would be a reasonable way to suppress the leak warning output.
<ikskuh>
use arena allocator
<cr1901_modern>
Okay works for me, I'll see how to use it
<ikskuh>
or even better (as told before): fix the library, make a PR, make everyone happy1
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<cr1901_modern>
I don't have the bandwidth to fix the library
<cr1901_modern>
I filed an issue a few weeks ago
<cr1901_modern>
In addition, someone smarter than me tried and failed to fix the issue :P
<cr1901_modern>
Right, since zig reached a nice milestone moving lots of code from C++ to zig land, I'm gonna try compling it.
<cr1901_modern>
Let's see what happens
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<cr1901_modern>
5.2GB for the self-hosted component... eep :o. But looks like I have enough RAM
<cr1901_modern>
Also is it normal for the compile of the self-hosted component to take several minutes? It's using 100% of a single core of my CPU. So it's doing work. Just curious
<ifreund>
I think that's not abnormal, the stage1 compiler is not efficient
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<cr1901_modern>
Finally linking. Took about 5 minutes.
<cr1901_modern>
Is the stage0/stage1/etc build process documented? I can of course gleam the basics by reading the source, but if there's docs I'd rather read those
<ifreund>
not too much to know, the stage0 compiler is written in C++ and is used to complie the parts of stage1 written in zig then linked with them to form stage1
<ifreund>
stage2 is written entirely in zig with an optional dependency on llvm
<ifreund>
stage3 is stage2 rebuilt using stage2
<cr1901_modern>
optional dep on llvm? Is this to support alternative backends in principle?
<tdeo>
stage2 doesn't actually have llvm support yet, it only supports its own backend
<frmdstryr>
Can I force zig to somehow do an 8 bit write to a 32bit register?
<frmdstryr>
I'm implementing SPI and it is always doing 16-bit writes
<frmdstryr>
So if I write 0xFF it's actually writing 0xFF and 0x00 on the wire
<ikskuh>
just do the cast as well?
<frmdstryr>
The value is already a u8?
<frmdstryr>
or do you mean cast the ptr to the register?
<ifreund>
yes that
<frmdstryr>
Dude... awesome! Hah, thanks!
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<Piraty>
jjsullivan: why did you list all the archs in the zig template (your cross PR) instead of just dropping archs= ?
<Piraty>
why exclude ppc* for example?
<jjsullivan>
I wasn't able to test if ppc works, and armv5te/mips wasn't compiling
<jjsullivan>
ppc is probably fine but idk about the others
<jjsullivan>
Piraty ^^
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<delaney>
Hi, I'm trying to get zig running on my work laptop which is unfortu
<delaney>
Lately a Mac... got it build from source finally but `zig init-exe` and `-lib` just hang forever
<pixelherodev>
cr1901_modern: LLVM dep is for optimizations, basically
<ifreund>
and for translate-c
<pixelherodev>
For now at least
<ifreund>
and zig cc
<cr1901_modern>
Is there an alternate IR that- hypothetically speaking, if I wanted to add a backend not in LLVM- I could generate code from in the zig stage 2 compiler?
<tdeo>
as i said stage2's not-llvm ir is the only ir, there's no llvm support yet :)
<ifreund>
cr1901_modern: sure, stage2 currently does not depend on llvm and generates code directly for multiple architectures
<ifreund>
debug builds of zig code will always be entirely self hosted using the bespoke codegen and incremental linking
<nikki93>
delaney: maybe you could try the master build at https://ziglang.org/download/ ? i've just been using the prebuilt ones for mac and it's worked fine for me. didn't try with the latest tho, probs about a couple weeks old