<corecode>
something odd happened to me with nextpnr - new version doesn't want to place SB_LED_DRV_CUR anymore
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<gatecat>
corecode: can you give me an example design and I'll have a look?
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<corecode>
i'll rebuild everything here to make sure that it still is the case
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<justchen1369>
hi
<justchen1369>
how could I synthesize a design down into just logic gates?
<justchen1369>
when I try I still end up with an sdffe node
<mwk>
yosys cannot synthesize FFs into logic gates; that'd be just asking for trouble since you really want them to be implemented via well-characterised pre-designed cells
<mwk>
if you really want to do it, you can provide your own mapping with techmap (perhaps together with dfflegalize and/or dffunmap to reduce the number of different cells you need to map)
<justchen1369>
FF?
<mwk>
flip-flops
<justchen1369>
ah
<justchen1369>
I realized quickly that yosys has a deceptively high learning curve haha