clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<lkcl> it's the default (best) arrangement for microwatt, as well, and works really well
<lkcl> chipdsgr: i've used ghdl+yosys for some *massive* conversions (output results in a 1.2 million line verilog file)
<lkcl> this was a subset of VHDL which was extracted from coriolis2 VLSI, post P&R.
<lkcl> worked great.
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