clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach3> yosys does not support $ceil ?
<promach3> ERROR: Found error in internal cell \ddr3_memory_controller.$ge$ddr3_memory_controller.sv:1061$73 ($ge) at kernel/rtlil.cc:991:
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<mwk> promach3: well you found a bug
<mwk> as a workaround, I think assigning the constant to an intermediate const-valued wire would help
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<promach3> mwk: what do you mean by **intermediate** const-valued wire ?
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<mwk> promach3: actually now that I look at it, I think the comparison isn't synthesizable verilog in the first place
<mwk> because it involves a floating point comparison
<promach3> yup, your suggested countermeasure also does not work
<promach3> <mwk "because it involves a floating p"> I suppose this is also a bug ?
<mwk> and the proper fix would be to write "localparam [31:0] TIME_TRFC = $ceil(...);"
<mwk> so that it'll be cast to integer
<mwk> no, this is not a bug
<mwk> it's just that floating point operations are not synthesizable
<mwk> because they don't map to logic circuits without major effort
<promach3> you mean add `[31:0]` ?
<mwk> yes
<promach3> let me try
<mwk> and btw by intermediate wire I meant something like "wire [31:0] tmp = 2.0; assign O = A < tmp;"
<mwk> but adding the type directly on localparam is superior
<promach3> ok, cool thanks mwk
<promach3> mwk: ok, now I could pass yosys check without errors. How do I pass yosys synthesis result to Xilinx ISE for place-and-route for Spartan-6 ?
<mwk> there's an example in yosys tree
<mwk> you'll need to write your own UCF of course, but the same synthesis script should work
<mwk> (well, that and fix the part number)
<promach3> ok, thanks mwk
<promach3> mwk: are you familiar with DDR ? May I ask some advice on setting constraints for `DQ` and `DQS` signals ?
<promach3> they are both `inout` signals
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<tpb> Title: DDR接口时序实例 - 春风一郎 - 博客园 (at www.cnblogs.com)
<promach3> mwk: Why the example you had given just now does not include SDC constraint file ?
<mwk> this is xilinx ISE, you generally use UCF constraints
<mwk> or at least they were enough for my little example
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