<AnonToday>
hello people. I have the versa board with 100mhz clock. However, my design will only run at 50mhz. do I need to use ecppll? if so are there any examples of how to do this?
<agg>
AnonToday: if you use the `ecppll` tool that comes with prjtrellis, you can use the -f argument to get it to write a verilog instantiation of the EHXPLLL module
<agg>
e.g. ecppll -i 100 -o 50 -f /dev/stdout
<AnonToday>
thanks I will check that out
<agg>
and yea, the pll is a good way to generate a 50MHz clock from the 100MHz input clock
<agg>
the lattice document TN1263 has some more tails on the pll, too
<AnonToday>
the generated ppl has this `locked` output. do I need to do anything with that?
<agg>
I don't believe it's necessary
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<mwk>
AnonToday: in general it's a good idea to keep your logic in reset until the clock is stable, so using the locked output to generate a reset is a good idea
<AnonToday>
well it seems to work without that but yeah I'll consider adding that. I guess it would be reset=!locked
<AnonToday>
so I got my 16-bit soft processor to run on versa using a fully open-source toolchain. I initially wrote the design years ago for xilinx and used proprietary tools at that time
<AnonToday>
I should make clear that what I meant was the design was targeting xilinx fpgas, not any other form of connection with xilinx
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<mwk>
reset would be !locked, but put it through a synchronizer as well
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