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<wolfspraul>
a small fpgatools update - I think my next target after blinking_led will be the j1 mini-core
<wolfspraul>
hopefully I can finish the blinking_led in about 1 more week
<wolfspraul>
that's all :-)
<wpwrak>
whee ! the blinking LED is the creation of life in a new universe. a core is merely evolution :)
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<wolfspraul>
that is the final version of blinking_led, only that the engine underneath does not yet generate a working bitstream...
<wolfspraul>
(and at the top I added a little verilog equivalent for comparison and documentation)
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<wolfspraul>
oh actually, I just notice it's not the final .c yet. the clock network is there, but some other networks are missing...
<wolfspraul>
more work in fnet_autoroute() :-)
<wpwrak>
hmm, quite a bit of redundancy
<wpwrak>
may look better if you use static initialization for logic_cfg
<wpwrak>
oh, and why y before x ? if they're coordinates, that seems rather confusing
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<wolfspraul>
yes I know, but there's a lot of fpga literature and sources that do that, although in general coordinates are confusing in the fpga world
<wolfspraul>
at the beginning I was thinking about this. x/y in the bottom left, x extending to the right and y upwards
<wpwrak>
ah, i see. historical convention then.
<wolfspraul>
but then I followed what looks like at least the largest 'convention'
<wolfspraul>
which is y going downwards (0 at the top), and y before x
<wolfspraul>
but then, you find everything, because i guess everybody stumbles upon this and then partially goes this or that way
<wpwrak>
heh :)
<wolfspraul>
oftentimes in the same sources you find some coordinates where y extends downwards, and others where it extends upwards
<wolfspraul>
yes, let's just say 'convention', although I am just trying to find a convention where maybe there is no convention
<wpwrak>
maybe you should just switch to polar coordinates :)
<wpwrak>
there you are ;-)
<wolfspraul>
y before x, y increasing downwards, x increasing rightwards
<wolfspraul>
at least fpgatools has only 1 coordinate system, some other popular fpga tools have >10 :-)
<wolfspraul>
static init for logic_cfg, sure
<wolfspraul>
I am not focusing on that 'higher' layer right now that much
<wpwrak>
(10 dimensions) sounds like string theory :)
<wolfspraul>
well the different types/categories of things each have their own coordinates
<wolfspraul>
so X2 'logic col' is one right of X1 'logic col'
<wolfspraul>
but there may be a X0 bram col in between :-)
<wpwrak>
(static init) actually, i see that it's more complicated since you carry over a lot of information from step to step. you'd probably need some sort of preprocessor.
<wolfspraul>
yes
<wolfspraul>
no need right now, I focus on the engine underneath
<wolfspraul>
that .c is just the tip of the iceberg
<wolfspraul>
later on maybe I find a way to write a bison parser or so, or we plug fpgatools in as an iverilog backend...
<wolfspraul>
it does look a lot cleaner now though
<wolfspraul>
without the if(rc) checks
<wpwrak>
yeah, it's pretty smooth reading
<wolfspraul>
some more networks missing, the connections between the luts, and the outgoing led wire...
<wolfspraul>
maybe 1 week is too optimistic, he
<wolfspraul>
first get the led to blink...
<wolfspraul>
thanks for looking over it...
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<wpwrak>
i see that you often have (y, x, idx) groups. maybe they could go into a struct, to reduce the number of arguments ?
<wolfspraul>
yes
<wolfspraul>
the temptation of C++ looms over it, but we shall resist...
<wpwrak>
all the good things C++ tempts you with you can also do in C :)
<wolfspraul>
when it's time to bury the project and declare it a failure, I will introduce C++ templates and operator overloading one month in advance...
<wolfspraul>
then we can blame C++
<wolfspraul>
that's the secret plan B here...
<wpwrak>
maybe that's why C++ is so popular
<wpwrak>
well, its star seems to be sinking a bit. maybe developers have gotten better and don't have quite so many failed projects to explain
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