infobot has quit [Read error: Connection reset by peer]
infobot has joined #neo900
Kabouik has joined #neo900
Kabouik has quit [Remote host closed the connection]
paulk-collins has quit [Ping timeout: 260 seconds]
silviof has quit [Read error: Connection reset by peer]
knttl has quit [Remote host closed the connection]
paulk-collins has joined #neo900
chomwitt has joined #neo900
chainsawbike has quit [Ping timeout: 240 seconds]
chainsawbike has joined #neo900
<chomwitt>
aloxa from greece!!
<chomwitt>
so a nOOb question. why do we need Samsung PoP memory ? and why do we need PoP anyway if there is a risk involved..
_whitelogger has joined #neo900
xmn has quit [Quit: Leaving.]
l_bratch has quit [Ping timeout: 240 seconds]
chainsawbike has quit [Ping timeout: 240 seconds]
chainsawbike has joined #neo900
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined #neo900
neo900 has joined #neo900
neo900 is now known as Joerg-Neo900
Joerg-Neo900 has quit [Killed (orwell.freenode.net (Nickname regained by services))]
chomwitt has quit [Ping timeout: 240 seconds]
l_bratch has joined #neo900
jonsger has joined #neo900
freemangordon has quit [Read error: Connection reset by peer]
jonwil has joined #neo900
<atk>
chainsawbike: The samsung pop memory is used because of availability, you have to use what is available and fits what you need.
<atk>
whoops, wrong person
<atk>
where did chomwitt go
<DocScrutinizer05>
we already sourced the unobtainium 1GB RAM PoP chips, which make the Neo900 the only device in the world except Nokia N9 with 1GB RAM on a OMAP3
<DocScrutinizer05>
PoP is the way to save massive amounts of real estate on PCB
<DocScrutinizer05>
also simplifies PCB layout since you don't need any timing critical memory bus on your layout
<jonsger>
DocScrutinizer05: whats happend with neo900.org/git ?
<DocScrutinizer05>
jonsger: oops, maybe last reboot tore it down?
<jonsger>
502 bad gateway
<DocScrutinizer05>
yeah
<DocScrutinizer05>
I wonder which dang service to restart
<atk>
unobtanium 1GB RAM PoP chips.
chomwitt has joined #neo900
<DocScrutinizer05>
atk: well, try to find a source or datasheet for the PoP!
<atk>
So the only way to have gotten more than 1GiB of ram would be to have another chip on the PCB (non-PoP)
<atk>
(I'm not suggesting that you go for 2GiB of ram or anything, it's probably a bit too late
<DocScrutinizer05>
atk: OMAP3 can't adress >1GB of RAM
<atk>
ah
<atk>
Well, 1GiB is 4 times what the N900 has, so it's probably good enough
<atk>
as long as you don't go to any websites these days because browsing the web requires at least 16GiB of RAM.
<DocScrutinizer05>
you'd need stuff not used anymore since IBM PC to extend beyond 640kB RAM
<bencoh>
fun stuff for sure
<DocScrutinizer05>
PC had same problem with 640kB that OMAP has with 1GB
<DocScrutinizer05>
it's not exactly simple to tweak the OS to handle such paged shadow RAM
<DocScrutinizer05>
it *could* get done but is highly complex and slow
<ShadowJK>
I remember there used to be a trick to create a ramdisk out of graphics card memory, and then you put swap on that. (in linux). Maybe a similar strategy would be workable :-)
<bencoh>
uhuh
<DocScrutinizer05>
well, switching the memory bus between two banks is more intricate than just accessing GPU RAM and rededicate it to a ramdisk. When your spare bank is switched in, your CPU loses all access to the genuine RAM bank
<DocScrutinizer05>
so you need a sophisticated memory controller that mirrors a part of the RAM address range to allow CPU to access and run a minimal set of switching functionality no matter what's the RAM bank recently activated
<bencoh>
not exactly
<DocScrutinizer05>
and you need a data buffer in same mirrored range
<bencoh>
you can also do with a small onchip ram (or reuse cpu cache if no sram is available, but that's ... itchy :p) to install tlb there and run some minimal code to switch bank
<DocScrutinizer05>
basically this is what is usually accomplished by your CPU embedded MMU unit
<bencoh>
this is actually what some (most?) SoC do to switch DDR frequency and enter/exit self-refresh mode
<bencoh>
nope, it's done in software
<bencoh>
there is even code for that in linux (or in bootloader in case of psci support)
<DocScrutinizer05>
the SRAM on SoC is 64kB iirc
<bencoh>
which is quite a lot :)
<DocScrutinizer05>
sure, when you want to memmove byte by byte, nothing wrong with a 16k
<DocScrutinizer05>
the problem is you don't want to do the switching too frequently
<bencoh>
well that's usually what you do to switch bank or refresh mode... just write to a few registers to configure mux/pll/clock/ddr, wait a bit here and there
<DocScrutinizer05>
you can't run program text in bank#0 with data structures allocated in bank#1
<bencoh>
that'd be a pain yeah
<DocScrutinizer05>
well, technically you could, but that would slow down the system by factor 100 or more
<bencoh>
but there would be other mechanisms to avoid that
<bencoh>
although I'm pretty sure that just having one single program running from bank#1 would be a pain since kernel would still sit on #0
<bencoh>
and context switch would just be .... awfuly slow
<bencoh>
anyway :)
<DocScrutinizer05>
the MMU had to trigger an exception each time an address outside your current bank gets accessed, and you need to run a sw handler to fetch that byte
<DocScrutinizer05>
yep
<bencoh>
EBADIDEA
<DocScrutinizer05>
:-)
chomwitt has quit [Ping timeout: 240 seconds]
chomwitt has joined #neo900
<DocScrutinizer05>
what you need is basically augmenting to MMU serving code to not only handle the SoC internal MMU but keep the external hack chip in sync, so the external chip would know which memaddr to find in which bank
<DocScrutinizer05>
basically a hybrid between MMU handler and swap handler
jonsger has quit [Ping timeout: 240 seconds]
mzki has quit [Quit: leaving]
mzki has joined #neo900
Pali has joined #neo900
Pali has quit [Remote host closed the connection]
freemangordon has joined #neo900
norly has joined #neo900
AndrewX192 has quit [Remote host closed the connection]
<ravelo>
DocScrutinizer05, there is one more device that had 1GB RAM
<ravelo>
about 20 pieces of Gta04A5 exist with 1 GB RAM
chomwitt has quit [Remote host closed the connection]
norly has quit [Ping timeout: 255 seconds]
norly has joined #neo900
jonsger has joined #neo900
BridgeControl is now known as electronyc
AndrewX192 has joined #neo900
jonwil has quit [Quit: ChatZilla 0.9.93 [SeaMonkey 2.46/20161213183751]]
cc___ has quit [Quit: WeeChat 1.6]
electronyc has quit [Ping timeout: 268 seconds]
electronyc has joined #neo900
jonsger has quit [Ping timeout: 240 seconds]
Zero_Chaos has quit [Remote host closed the connection]
galiven_ has joined #neo900
DocScrutinizer05 has quit [Disconnected by services]