sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<_whitenotifier> [nmigen] RobertBaruch commented on issue #211: Right way to express a bundle of Signals? - https://git.io/Je3Nk
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<whitequark> ZirconiumX: yeah something like this
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<_whitenotifier> [nmigen] whitequark commented on issue #211: Right way to express a bundle of Signals? - https://git.io/Je3AQ
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<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/Je3x5
<_whitenotifier> [m-labs/nmigen] whitequark f6f0a7b - lib.fifo: simplify. NFC.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/587765499?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 83.07% (+0.24%) compared to a1bc2bb - https://codecov.io/gh/m-labs/nmigen/commit/f6f0a7b692dafbaf16ccab13c03c1e34e84ae8d6
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 82.83%) - https://codecov.io/gh/m-labs/nmigen/commit/f6f0a7b692dafbaf16ccab13c03c1e34e84ae8d6
<_whitenotifier> [nmigen] whitequark opened issue #219: AsyncFIFO[Buffered] initialization is unergonomic - https://git.io/Je3xb
<_whitenotifier> [nmigen] Success. 82.84% (+<.01%) compared to a1bc2bb - https://codecov.io/gh/m-labs/nmigen/commit/f6f0a7b692dafbaf16ccab13c03c1e34e84ae8d6
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/587765499?utm_source=github_status&utm_medium=notification
<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/Je3pO
<_whitenotifier> [m-labs/nmigen] whitequark a13a21c - hdl.ast: update docs. NFC.
<_whitenotifier> [m-labs/nmigen] whitequark 2dc6ae4 - lib.fifo: update docs. NFC.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/587770404?utm_source=github_status&utm_medium=notification
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<ZirconiumX> Well, altiobuf wants you to instantiate it before using it, and I don't much feel like dealing with *that*
<whitequark> instantiate what
<ZirconiumX> It's an IP core
<ZirconiumX> Error (12006): Node instance "$8" instantiates undefined entity "altiobuf". Ensure that required library paths are speci
<ZirconiumX> party IP, generate the synthesis files for the IP.
<ZirconiumX> fied correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-
<whitequark> isn't this a missing library path
<ZirconiumX> No, this is "Intel FPGA IP"
<ZirconiumX> Time for a different approach...
<_whitenotifier> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±9] https://git.io/Jesfx
<_whitenotifier> [m-labs/nmigen] whitequark 07a82ed - build.plat: NMIGEN_<toolchain>_env→NMIGEN_ENV_<toolchain>
<_whitenotifier> [m-labs/nmigen] whitequark 8050cfa - build.res: simplify clock constraints.
<_whitenotifier> [m-labs/nmigen] whitequark 3d62dac - vendor.lattice_ice40: add iCECube support.
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<_whitenotifier> [m-labs/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±8] https://git.io/JesJv
<_whitenotifier> [m-labs/nmigen-boards] whitequark cb0c2cd - Fix IO_STANDARD on all iCE40 boards.
<whitequark> ZirconiumX: is it case-sensitive?
<whitequark> the doc calls it ALTIOBUF, not altiobuf
<ZirconiumX> whitequark: It's lower case; I instantiated it manually to check
<whitequark> ah
<ZirconiumX> I'm going to try a different approach
<ZirconiumX> They have a lower-level primitive called alt_{in,out,io}buf
<ZirconiumX> Yes, they have an IP core called altiobuf and a primitive called alt_iobuf
<whitequark> ;w;
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<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/587857245?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Failure. 82.82% (-0.02%) compared to f6f0a7b - https://codecov.io/gh/m-labs/nmigen/commit/3d62dac1cbc3f0c74eb48d87bfe9340fdcb79776
<_whitenotifier> [nmigen] Success. Coverage not affected when comparing f6f0a7b...3d62dac - https://codecov.io/gh/m-labs/nmigen/commit/3d62dac1cbc3f0c74eb48d87bfe9340fdcb79776
<_whitenotifier> [nmigen] whitequark opened issue #220: Prune Yosys-internal attributes in emitted Verilog - https://git.io/JesJm
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<_whitenotifier> [nmigen] ZirconiumX commented on issue #220: Prune Yosys-internal attributes in emitted Verilog - https://git.io/JesJY
<_whitenotifier> [nmigen] daveshah1 commented on issue #220: Prune Yosys-internal attributes in emitted Verilog - https://git.io/JesJs
<_whitenotifier> [nmigen] whitequark commented on issue #220: Prune Yosys-internal attributes in emitted Verilog - https://git.io/JesJZ
<_whitenotifier> [nmigen] whitequark commented on issue #220: Prune Yosys-internal attributes in emitted Verilog - https://git.io/JesJE
<_whitenotifier> [nmigen] daveshah1 commented on issue #220: Prune Yosys-internal attributes in emitted Verilog - https://git.io/JesJu
<ZirconiumX> whitequark: I have gotten an alt_outbuf based blinky to build and run
<ZirconiumX> For whatever that's worth
<whitequark> nice
<ZirconiumX> Is there something I can use to test SDR?
<whitequark> you'd need to add some logic
<whitequark> ideally watch it with a scope
<_whitenotifier> [nmigen] RobertBaruch commented on issue #211: Right way to express a bundle of Signals? - https://git.io/JesUf
<_whitenotifier> [nmigen] RobertBaruch closed issue #211: Right way to express a bundle of Signals? - https://git.io/Je3mW
<_whitenotifier> [nmigen] ZirconiumX opened pull request #221: vendor.altera: use buffer primitives - https://git.io/JesUg
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/587878415?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] codecov[bot] commented on pull request #221: vendor.altera: use buffer primitives - https://git.io/JesUV
<_whitenotifier> [nmigen] Success. Coverage not affected when comparing 376180f...9ffedac - https://codecov.io/gh/m-labs/nmigen/compare/376180f21e9ad03b3df10bfc4ab223aea02bdf3e...9ffedac507aac9060f122490a1a95f9761cc17a6
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/587878415?utm_source=github_status&utm_medium=notification
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<_whitenotifier> [nmigen] peteut reviewed pull request #221 commit - https://git.io/JesTa
<_whitenotifier> [nmigen] peteut reviewed pull request #221 commit - https://git.io/JesTw
<_whitenotifier> [nmigen] RobertBaruch opened issue #222: Consider arrays in Records - https://git.io/JesIs
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<_whitenotifier> [nmigen] ZirconiumX commented on pull request #221: vendor.altera: use buffer primitives - https://git.io/JesL5
<_whitenotifier> [nmigen] RobertBaruch opened issue #223: Consider enums in Records - https://git.io/JesLA
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