sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<_whitenotifier> [nmigen] RobertBaruch opened pull request #204: Adds Value.matches - https://git.io/JemSc
<_whitenotifier> [nmigen] Failure. The Travis CI build failed - https://travis-ci.org/m-labs/nmigen/builds/583939680?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Failure. The Travis CI build failed - https://travis-ci.org/m-labs/nmigen/builds/583939680?utm_source=github_status&utm_medium=notification
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<harryho> whitequark: Thanks!
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<_whitenotifier> [nmigen] RobertBaruch synchronize pull request #204: Adds Value.matches - https://git.io/JemSc
<_whitenotifier> [nmigen] codecov[bot] commented on pull request #204: Adds Value.matches - https://git.io/Jem92
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/583969566?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/583969566?utm_source=github_status&utm_medium=notification
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<mtrbot-ml> [mattermost] <sb10q> @hartytp how is thermostat testing coming along?
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<mtrbot-ml> [mattermost] <charlesbaynham> Hi all, what's the recommended way to quit an Experiment in progress? At the moment I'm raising a SystemExit, but is there a better way?
<mtrbot-ml> [mattermost] <sb10q> return
<_whitenotifier> [nmigen] whitequark reviewed pull request #204 commit - https://git.io/JembU
<_whitenotifier> [nmigen] whitequark reviewed pull request #204 commit - https://git.io/Jembt
<mtrbot-ml> [mattermost] <charlesbaynham> Makes sense, thanks
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<kernlbob_> Are nMigen clock domain names global?
<whitequark> when a new clock domain is added, it's propagated to the rest of the design, yes
<kernlbob_> whitequark: That makes it easy, thanks.
<kernlbob_> I keep thinking I'm almost to the point where I can stop asking nMigen questions and go write some code.
<kernlbob_> But...
<kernlbob_> I have a PLL. It creates a clock domain. Do I have to use `m.d.name_of_domain` throughout the design because of that?
<kernlbob_> Is there a way to use library modules?
<whitequark> yes, use something like `m.submodules += DomainRenamer("pll_domain")(UART(...))`
<whitequark> or if most of your design is clocked by the PLL, you can make that your sync domain
<kernlbob_> Do I make it the sync domain simply by naming it 'sync'?
<whitequark> yeah
<whitequark> there's nothing special about sync
<whitequark> other than it being the default in a number of places
<kernlbob_> I was reading through the module creation code in nmigen/hdl/dsl.py, and it looks like "sync" is not created until it is used?
<whitequark> I'm not sure what you're asking
<kernlbob_> If the design does not override "sync", when is sync domain created?
<whitequark> build.plat.create_missing_domain
<kernlbob_> Yeah, that's what I suspected. Thanks.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±6] https://git.io/JemxO
<_whitenotifier> [m-labs/nmigen] whitequark 8f659b6 - lib.cdc: adjust MultiReg for new CDC primitive conventions.
<_whitenotifier> [m-labs/nmigen] whitequark 9893e3c - lib.cdc: adjust ResetSynchronizer for new CDC primitive conventions.
<_whitenotifier> [m-labs/nmigen] whitequark 73244f2 - lib.io: style. NFC.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/Jemxn
<_whitenotifier> [m-labs/nmigen] whitequark 2d2ab6e - lib.cdc: make domain properties private.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584155674?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 82.93% (+0.13%) compared to 8c30147 - https://codecov.io/gh/m-labs/nmigen/commit/73244f2bd25b41c84d0cd55b5065464d596df773
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 82.8%) - https://codecov.io/gh/m-labs/nmigen/commit/73244f2bd25b41c84d0cd55b5065464d596df773
<_whitenotifier> [nmigen] Success. 82.8% (+0%) compared to 8c30147 - https://codecov.io/gh/m-labs/nmigen/commit/73244f2bd25b41c84d0cd55b5065464d596df773
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584155674?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584157423?utm_source=github_status&utm_medium=notification
<mtrbot-ml> [mattermost] <astro> aw, again, could somebody at the lab please reset the ionpak-thermostat? the debugger isn't working again. @sb10q @harryho @whitequark
<mtrbot-ml> [mattermost] <astro> luckily I was able to test my latest progress before it froze
<whitequark> sb: you should connect the device we have for resetting stuff to thermostat
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584157423?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] whitequark commented on issue #147: Reduce-op (reduce-or, reduce-and, reduce-xor) - https://git.io/Jempf
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<mtrbot-ml> [mattermost] <astro> that's a great idea
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<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/Jempn
<_whitenotifier> [m-labs/nmigen] whitequark 2c34b1f - README: update Yosys version requirement.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584174039?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584174039?utm_source=github_status&utm_medium=notification
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<_whitenotifier> [nmigen] jordens commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/Jemh3
<_whitenotifier> [nmigen] emilazy commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/Jemhs
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<_whitenotifier> [nmigen] whitequark commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/JemhR
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<_whitenotifier> [nmigen] jordens commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/Jemh7
<_whitenotifier> [nmigen] jordens commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/JemhF
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<_whitenotifier> [nmigen] whitequark commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/JemjL
<_whitenotifier> [nmigen] mithro commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/JemjG
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<_whitenotifier> [nmigen] emilazy commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/Jemjc
<_whitenotifier> [nmigen] whitequark commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/JemjC
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<_whitenotifier> [nmigen] jordens commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/Jemju
<_whitenotifier> [nmigen] whitequark commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/Jemjo
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<mtrbot-ml> [mattermost] <sb10q> except it's not that simple (as usual): the jtag cable might need a power cycle as well as or instead of thermostat, the thermostat is on PoE right now, and if I use one 12V adapters that I have they contain big capacitors that retain power longer than the delay in the power-cycler
<mtrbot-ml> [mattermost] <sb10q> @hartytp ping re. tests
<mtrbot-ml> [mattermost] <sb10q> @astro what do we need an allocator for?
<mtrbot-ml> [mattermost] <hartytp> working on it
<whitequark> sb: btw where is my blackmagic probe
<whitequark> are you using it there?
<mtrbot-ml> [mattermost] <sb10q> no, and I have never seen it
<mtrbot-ml> [mattermost] <sb10q> afaik you never brought it
<mtrbot-ml> [mattermost] <hartytp> (have been slow since getting the final wrinkles out of booster pushed it off the top of my priority list)
<mtrbot-ml> [mattermost] <sb10q> well those tests are blocking hardware v2 production and also the current device is wasting time due to jtag bugs
<whitequark> sb: i gave it to you before
<whitequark> i don't have it, haven't had for a year...
<mtrbot-ml> [mattermost] <hartytp> I know, working on it
<whitequark> if you lost it that's very annoying because it's expensive
<mtrbot-ml> [mattermost] <sb10q> I have never had it
<whitequark> I've left it at the lab the previous spring so you could debug your stuff AFAIK
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<rjo[m]> cjbe: if you want to dig into ITM on stm32h7, here is the code that i ended up with back in april. https://gist.github.com/jordens/7cdf6748573088cf1cd7cd2ae35e3fae
<mtrbot-ml> [mattermost] <hartytp> @astro re PID, should be gain before integrate, no?
<whitequark> sb0: actually, once you get your glasgow, you could just use that as a debugger
<whitequark> debugger/tracer
<mtrbot-ml> [mattermost] <hartytp> (don't want an output kick if you change Ki)
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<mtrbot-ml> [mattermost] <cjbe> @rjo thanks for that gist
<mtrbot-ml> [mattermost] <cjbe> @rjo I am thinking about how to implement a command parser on Stabilizer, for things like setting AFE gains, querying firmware versions, etc
<mtrbot-ml> [mattermost] <cjbe> The restrictions on serde-json-core seem to forbid useful rust-type enums, so it seems like the least worse option is to have a 'command' type struct which has a c-like type enum, and carries a json payload
<mtrbot-ml> [mattermost] <cjbe> Do you have any better ideas than this?
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<ZirconiumX> How does one express a range of values with a Case statement?
<ZirconiumX> Since range(A, B) produces a range object
<whitequark> with Case(*range(A, B)):
<ZirconiumX> Thank you
<ZirconiumX> ...I broke pysim
<ZirconiumX> ...Maybe I need a different approach to not produce *quite* so many variables
<whitequark> broke?
<whitequark> how?
<whitequark> seems like a bug
<ZirconiumX> So, my clever idea was to build a LUT by using `range`
<ZirconiumX> Unfortunately it appears pysim doesn't handle you trying to match 4,096 values in said LUT
* ZirconiumX is not smart
<ZirconiumX> I'll try m.If instead
<whitequark> oh.
<whitequark> you probably want an Array.
<whitequark> not If or Case.
<whitequark> If and Case are the same thing anyway
<ZirconiumX> Well, my assumption is that pysim will handle "if x >= LOWER_BOUND and x < UPPER_BOUND" more gracefully than "if x == LOWER_BOUND || x == LOWER_BOUND + 1 || ..."
<whitequark> ohhh
<whitequark> that's less generic than a LUT
<ZirconiumX> It's essentially a 16-bit array for the fixed-point reciprocal of a number
<whitequark> that sounds like something you'd use an Array or even a Memory for.
<whitequark> probably Memory.
<ZirconiumX> Unfortunately Quartus' BRAM (BROM?) inference code kinda sucks
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/JeYJC
<_whitenotifier> [m-labs/nmigen] whitequark 1c091e6 - lib.fifo: remove SyncFIFO.replace.
<whitequark> does it?
<ZirconiumX> They really want you to instantiate an altsyncram primitive, despite the best attempts of their inference engine
<whitequark> that's just every vendor
<whitequark> does it not actually work with nmigen's output?
<ZirconiumX> I haven't tried using an nmigen Memory yet, but my general experience with Verilog is that Quartus doesn't understand what you're trying to do
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584289901?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. Absolute coverage decreased by -0.02% but relative coverage increased by +17.19% compared to 2c34b1f - https://codecov.io/gh/m-labs/nmigen/commit/1c091e67a42208c2a4f3e8bef51d24e906c4173c
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 82.8%) - https://codecov.io/gh/m-labs/nmigen/commit/1c091e67a42208c2a4f3e8bef51d24e906c4173c
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584289901?utm_source=github_status&utm_medium=notification
<whitequark> well, I looked at their docs just now and nMigen should emit the exact pattern they suggest
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<whitequark> at least for non-transparent memories
<whitequark> but you don't need a transparent memory, you're making a ROM
<ZirconiumX> So, uh, the ROM might not have been the smartest of ideas, because now pysim is running at a crawl.
<ZirconiumX> But it's funny to watch it spew out the ROM 3 times
<whitequark> yeah, pysim will be slow at this no matter what you do.
<ZirconiumX> And Yosys takes a while to parse the resulting file
<whitequark> hm
<ZirconiumX> Well, generate RTLIL rather
<whitequark> link to verilog?
<ZirconiumX> lofty@ramen:~/gs$ wc -l line.v
<ZirconiumX> 198398 line.v
<ZirconiumX> Mmm
<ZirconiumX> The worst feeling is looking at the Verilog and noticing the ROM is very, very wrong
<ZirconiumX> Right, with a fixed ROM, it's probably better if I send you the python instead of the Verilog
<whitequark> well, if the verilog is 200k line long...
<whitequark> why is it 200k anyway
<whitequark> and not 64k
<ZirconiumX> I instantiate the module 3 times for the 3 colour channels
<ZirconiumX> So it produces 64k * 3 = 192k of ROM
<whitequark> btw if you let yosys read RTLIL directly it won't be that slow.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/JeYJy
<_whitenotifier> [m-labs/nmigen] whitequark b92e967 - lib.fifo: make fwft a keyword-only argument.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584298624?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 82.91% (+0.13%) compared to 1c091e6 - https://codecov.io/gh/m-labs/nmigen/commit/b92e967b7815e6115f0a833efb8246dd63681d6b
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 82.78%) - https://codecov.io/gh/m-labs/nmigen/commit/b92e967b7815e6115f0a833efb8246dd63681d6b
<ZirconiumX> Indeed, though synth_ecp5 apparently pruning my ROM is not a great sign
<ZirconiumX> Oh, I should specify it as a port
<ZirconiumX> That might be why :P
<_whitenotifier> [nmigen] Success. 82.78% (+0%) compared to 1c091e6 - https://codecov.io/gh/m-labs/nmigen/commit/b92e967b7815e6115f0a833efb8246dd63681d6b
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584298624?utm_source=github_status&utm_medium=notification
<ZirconiumX> Given the increase in LUT4s, I'm *assuming* it's put the ROM in LUTRAM
<whitequark> it should be a synchronous read port
<whitequark> not sure why it'd put a 64K of ROM in LUTRAM
<ZirconiumX> So, transparent=True?
<whitequark> no, has nothing to do with transparency
<whitequark> domain="sync", which is the default
<ZirconiumX> Okay
<ZirconiumX> Yeah it seems Yosys wants to put this in LUTRAM instead of BRAM
<ZirconiumX> I tried synth_ice40, synth_ecp5 and synth_xilinx
<ZirconiumX> All of them went into LUTRAM
<whitequark> interesting
<whitequark> kinda weird
<ZirconiumX> Anyway, let's see what Quartus makes of this.
<whitequark> try transparent=False just to see if it does anything?
<ZirconiumX> Doesn't seem like it
<whitequark> thought so
<ZirconiumX> Also I like how I've synthesised for 3 different FPGA architectures and Quartus hasn't even finished with this
<ZirconiumX> s/architectures/architectures with Yosys/
<_whitenotifier> [nmigen] whitequark created branch lib.fifo-conventions - https://git.io/fhUU5
<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to lib.fifo-conventions [+0/-0/±4] https://git.io/JeYU1
<_whitenotifier> [m-labs/nmigen] whitequark e3122ed - lib.fifo: adjust properties to have consistent naming.
<ZirconiumX> It appears Quartus really does not like people inlining 64k ROMs
<_whitenotifier> [m-labs/nmigen] whitequark da61076 - lib.fifo: adjust for new CDC primitive conventions.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JeYUD
<_whitenotifier> [m-labs/nmigen] whitequark 42805ad - hdl.mem: use keyword-only arguments as appropriate.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584306677?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. No report found to compare against - https://codecov.io/gh/m-labs/nmigen/commit/da61076b57adee8250f0ca861065beb3d25e7a5a
<_whitenotifier> [nmigen] Success. No report found to compare against - https://codecov.io/gh/m-labs/nmigen/commit/da61076b57adee8250f0ca861065beb3d25e7a5a
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584306677?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] whitequark commented on issue #97: Bikeshed: conventions for CDC primitives - https://git.io/JeYUy
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584306683?utm_source=github_status&utm_medium=notification
<ZirconiumX> Okay this ROM really is not practical to develop with
<_whitenotifier> [nmigen] Success. 82.91% (+0.13%) compared to b92e967 - https://codecov.io/gh/m-labs/nmigen/commit/42805ad95974b14aaf88b9e418d23559ab92bee3
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 82.78%) - https://codecov.io/gh/m-labs/nmigen/commit/42805ad95974b14aaf88b9e418d23559ab92bee3
<whitequark> lol
<ZirconiumX> I'm not going to wait 10 minutes at 2% compiled while it elaborates the ROM
<_whitenotifier> [nmigen] Success. 82.78% (+0%) compared to b92e967 - https://codecov.io/gh/m-labs/nmigen/commit/42805ad95974b14aaf88b9e418d23559ab92bee3
<ZirconiumX> Combinational logic it is
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584306683?utm_source=github_status&utm_medium=notification
<_whitenotifier> [smoltcp] cjbe opened pull request #306: Only use first 3 DHCP advertised DNS servers (cf #305) - https://git.io/JeYUd
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<_whitenotifier> [smoltcp] Success. The Travis CI build passed - https://travis-ci.org/m-labs/smoltcp/builds/584311436?utm_source=github_status&utm_medium=notification
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<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±4] https://git.io/JeYIc
<_whitenotifier> [m-labs/nmigen] whitequark c8f8c09 - vendor.xilinx_7series: Vivado requires bash on *nix as well.
<_whitenotifier> [m-labs/nmigen] whitequark 9ea3ff7 - build.plat: bypass tool detection if NMIGEN_*_env is set.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584351142?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 82.85% (+0.07%) compared to 42805ad - https://codecov.io/gh/m-labs/nmigen/commit/9ea3ff7ae2fb14f862697ebd5fac03679125bb7b
<_whitenotifier> [nmigen] Failure. 14.28% of diff hit (target 82.78%) - https://codecov.io/gh/m-labs/nmigen/commit/9ea3ff7ae2fb14f862697ebd5fac03679125bb7b
<_whitenotifier> [nmigen] Failure. 82.72% (-0.06%) compared to 42805ad - https://codecov.io/gh/m-labs/nmigen/commit/9ea3ff7ae2fb14f862697ebd5fac03679125bb7b
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584351142?utm_source=github_status&utm_medium=notification
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<_whitenotifier> [nmigen] Success. 82.8% remains the same compared to 2d2ab6e - https://codecov.io/gh/m-labs/nmigen/commit/2c34b1f9473a6b5a9f1e1c5a56dd17d821c29219
<_whitenotifier> [nmigen] Success. 82.8% remains the same compared to 2d2ab6e - https://codecov.io/gh/m-labs/nmigen/commit/2c34b1f9473a6b5a9f1e1c5a56dd17d821c29219
<_whitenotifier> [nmigen] Success. 82.8% remains the same compared to 2d2ab6e - https://codecov.io/gh/m-labs/nmigen/commit/2c34b1f9473a6b5a9f1e1c5a56dd17d821c29219
<_whitenotifier> [nmigen] Success. 82.8% remains the same compared to 2d2ab6e - https://codecov.io/gh/m-labs/nmigen/commit/2c34b1f9473a6b5a9f1e1c5a56dd17d821c29219
<_whitenotifier> [nmigen] Success. Coverage not affected when comparing 2d2ab6e...2c34b1f - https://codecov.io/gh/m-labs/nmigen/commit/2c34b1f9473a6b5a9f1e1c5a56dd17d821c29219
<_whitenotifier> [nmigen] Success. Coverage not affected when comparing 2d2ab6e...2c34b1f - https://codecov.io/gh/m-labs/nmigen/commit/2c34b1f9473a6b5a9f1e1c5a56dd17d821c29219
<_whitenotifier> [nmigen] Success. Coverage not affected when comparing 2d2ab6e...2c34b1f - https://codecov.io/gh/m-labs/nmigen/commit/2c34b1f9473a6b5a9f1e1c5a56dd17d821c29219
<_whitenotifier> [nmigen] Success. Coverage not affected when comparing 2d2ab6e...2c34b1f - https://codecov.io/gh/m-labs/nmigen/commit/2c34b1f9473a6b5a9f1e1c5a56dd17d821c29219
<_whitenotifier> [nmigen] Success. Coverage not affected when comparing 2d2ab6e...2c34b1f - https://codecov.io/gh/m-labs/nmigen/commit/2c34b1f9473a6b5a9f1e1c5a56dd17d821c29219