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<
mtrbot-ml >
[mattermost] <sb10q> @rjo are you still using the old novogorny in opticlock?
03:50
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whitequark >
harryho: looking into nmigen-stdio now
03:55
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harryho >
whitequark: Thanks. @sb0 Where should CSR abstractions go?
03:58
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whitequark >
I think per discussion before they should go to nmigen-cores
03:58
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whitequark >
I can create and populate that repo as well
04:02
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harryho >
I see. I'm trying to finish working on CSR myself by Tuesday.
04:03
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whitequark >
out of curiosity, what's your background?
04:07
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harryho >
I'm final-year Computer Engineering undergrad at HKUST. My previous work in electronics were mostly with STM32, Arduino and Raspberry Pi.
04:07
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whitequark >
ah, makes sense
04:07
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harryho >
Before getting into M-Labs I have never worked on or been taught about FPGAs.
04:08
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harryho >
So I'm learning in my own pace right now :D
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whitequark >
hm, we should just get rid of versioneer, it never works correctly
04:18
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whitequark >
give me a sec
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whitequark >
ok, very nice
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_whitenotifier >
[m-labs/nmigen] whitequark 284b533 - setup: replace versioneer with setuptools_scm.
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_whitenotifier >
[m-labs/nmigen-boards] whitequark f137570 - setup: replace versioneer with setuptools_scm.
05:30
<
_whitenotifier >
[m-labs/nmigen] whitequark 38831ab - Fix .gitignore.
05:37
<
_whitenotifier >
[GitHub] Avoid administrative distraction.
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_whitenotifier >
[m-labs/nmigen] whitequark d071adb - Remove nmigen.lib from prelude.
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_whitenotifier >
[m-labs/nmigen] whitequark 5e9587b - Remove nmigen.lib from prelude.
07:33
<
_whitenotifier >
[m-labs/nmigen-stdio] whitequark e8dc706 - serial: WIP
07:36
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whitequark >
harryho: here's a rough example of how I imagine an UART should look like
07:36
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whitequark >
note the ability to pass pins--something like `AsyncSerial(pins=platform.request("uart"))` should seamlessly work
07:37
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whitequark >
conversely, rdy/ack signaling should work in such a way that it can be wired directly to a FIFO
07:37
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whitequark >
(in the serial branch)
07:50
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harryho >
whitequark: Thanks a lot! I first recalled a similar usage of FSM abstraction on nmigen/examples/basic/fsm.py, although some states from that example aren't in nmigen-cores right now. I think I can figure that out.
08:02
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whitequark >
harryho: yes, I rewrote the UART to use a much simpler (in terms of generated logic) implementation
08:02
<
whitequark >
i don't think it actually ever matters in practice, it's just a bit more elegant
08:03
<
whitequark >
and it'd also be easier to add parity (no new states, just add one bit and one assignment/comparison)
08:05
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whitequark >
harryho: oh yeah, let me create nmigen-cores too.
08:06
<
whitequark >
or was it nmigen-soc? let me check
08:06
<
whitequark >
yeah, nmigen-soc is probably better, by analogy with misoc
08:09
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harryho >
I agree :] And I thought something was wrong caz GitHub redirected me from nmigen-cores to nmigen-stdio
08:09
<
whitequark >
yeah, it was renamed
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whitequark >
harryho: done
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harryho >
whitequark: Many thanks!
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mithro >
What is that nix based build system that sb0 has been working on?
14:03
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whitequark >
heavyx
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