sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1065: > NB if you don't actively drive a clock input then it's well within its rights to free oscillate at any frequency it likes. This is quite common, and can be very sensitive to PVT. If you clock logic from a floating enabled clock input then you could see anything, I don't think there is much you can infer from that observation.... https://github.com/m-labs/art
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1065: > NB if you don't actively drive a clock input then it's well within its rights to free oscillate at any frequency it likes. This is quite common, and can be very sensitive to PVT. If you clock logic from a floating enabled clock input then you could see anything, I don't think there is much you can infer from that observation.... https://github.com/m-labs/art
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1065: > NB if you don't actively drive a clock input then it's well within its rights to free oscillate at any frequency it likes. This is quite common, and can be very sensitive to PVT. If you clock logic from a floating enabled clock input then you could see anything, I don't think there is much you can infer from that observation.... https://github.com/m-labs/art
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<sb0_>
we have a -1C FPGA on Sayma AMC, but the schematics says VCCINT is 0.9V
<sb0_>
-1C requires 0.95
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<sb0>
well the sayma schematics don't seem to match the board
<sb0>
there is an additional 10 ohm resistor in series with R243 and R244, on the other side
<sb0>
I can confirm that R243 and R244 are 3.3k and 2k, as Greg posted in the issue
<sb0>
and not 2*3.3k like the schematics says
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1065: @gkasprow Please help me locate the voltage-setting resistors. The two resistors that @jordens mentions are 3.3K and 2K, which is consistent with https://github.com/sinara-hw/sinara/issues/209#issuecomment-332620991. But there is an additional 10-ohm resistor in series with them on the other side of the board, which is not on the schematics. What is going on?
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1065: @gkasprow Please help me locate the voltage-setting resistors. The two resistors that @jordens mentions are 3.3K and 2K on the low-voltage board, which is consistent with https://github.com/sinara-hw/sinara/issues/209#issuecomment-332620991. But there is an additional 10-ohm resistor in series with them on the other side of the board, which is not on the schematic
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1065: @gkasprow Please help me locate the voltage-setting resistors. The two resistors that @jordens mentions are 3.3K and 2K on the low-voltage/crashing board, which is consistent with https://github.com/sinara-hw/sinara/issues/209#issuecomment-332620991. But there is an additional 10-ohm resistor in series with them on the other side of the board, which is not on the
<sb0>
rjo, do you know anything about that 10-ohm resistor?
<sb0>
I plan to set R243 and R244 to 3.3K + 2.7K. does that sound OK?
<rjo>
sb0: there are a lot of things in series with r244: it's at the very busy p0v9 node. to clarify: you measured 10R between R315 and R244?
<sb0>
rjo, yes
<rjo>
and i generally wouldn't trust the xadc voltages since it's broken.
<rjo>
ok. then yes. that's weird and inconsistent with the schematics.
<rjo>
sb0: that would give you .96v. you can remove r315 and r316 for testing if you don't want to burn the fpga.
<rjo>
but i don't know how much the fpga dislikes vccint=0 and whether the sequencing will stop the rest from powering up.
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<sb0>
the sequencing will not prevent the rest from powering up, it's triggered by PGOOD_P0V9 which is generated by the switching regulator IC33
<sb0>
it doesn't seem like the FPGA likes low VCCINT with the other supplies running, e.g. "More than 3A of current draw on the VCCAUX supply has been observed as VCCINT falls in the range of 0.75V and 0.5V" (https://www.xilinx.com/support/answers/62113.html)
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<hartytp>
sb0: note that in the photo you posted (which matches my AMC) the silk label for R315 seems to be wrong
<hartytp>
well, doesn't match the schematic
<rjo>
hartytp: r315 is the fat 0R the label is just offset, like r316
<hartytp>
maybe
<hartytp>
as sb0 says, the schematics don't match the board
<hartytp>
(R244 does not seem to connect directly to R315)
<hartytp>
so, it's either that the silk for those power resistors has ended up in the wrong place or that some component names have changed between silk and schematic
<hartytp>
either way, the current silk is (at very best) quite misleading
<hartytp>
i suspect that the pdf schematics on git hub are out of date
<sb0>
rjo, FYI using the SATA connector on Kasli with DRTIO works just fine (and without GTP annoyances)
<sb0>
this also works with the 10-port Sayma master, using the RTM-SATA breakout that Greg made, and a regular SATA cable
<GitHub-m-labs>
[artiq] hartytp commented on issue #1080: @marmeladapk that's what I thought, thanks for confirming. It was a long shot, but I wondered if this was some SI issue related to the low clock amplitudes using LVDS outputs in combination with 200R LVPECL bias resistors. If you've tested that then I won't bother looking at it again. https://github.com/m-labs/artiq/issues/1080#issuecomment-400255754
<hartytp>
sb0: cool
<hartytp>
if we can package that up nicely, it would be quite useful
<sb0>
rjo, how certain are you that those two resistors at the top right are indeed R243/R244? should I go ahead, replace them, and run the crash-kernel - or keep waiting for Greg?
<rjo>
sb0: 90% but since i can't explain that other resistor on the back nor the oone that's dnp'ed, i'd just wait.
<rjo>
sb0: btw. i noticed that vivado has a tool to hunt down and analyze all CDCs in a design. and it classifies some of the ones we have (iirc the ARS) as "unknown 1-bit synchronizer" and complains about them. others have comb logic in front of them which i am not so worried about. could you at some point have a look and review those?
<sb0>
can you open an issue?
<rjo>
sure.
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1061: I've disabled the overclocking in the BIOS on ``build.lab.m-labs.hk`` so it should be stable now. We should move the builds to that faster machine. https://github.com/m-labs/artiq/issues/1061#issuecomment-400264812
<rjo>
i wonder what the (apparently known, specified, and finite) "device lifetime" is.
<hartytp>
sb0: I know Sayma is eating up all your time right now (and have a lot of sympathy for that, as it's doing the same to me)
<hartytp>
but, what's the timeline for DRTIO switching?
<hartytp>
I'm getting chased to close that order down by our finance team
<sb0>
do they have any particular deadline?
<hartytp>
I can put them off for a while
<hartytp>
but it would be good to know what your thoughts are about this
<hartytp>
e.g. where is it in your pipeline
<hartytp>
and how long do you anticipate it taking once you start on it
<hartytp>
I want to make sure that I have realistic expectations here
<sb0>
that would be after sayma is in a satisfactory state, and after grabber firmware
<hartytp>
okay. "sayma is in a satisfactory state" is a bit open ended atm
<sb0>
yes.
<hartytp>
anyway, afaict, the next step for sayma if the vccint doesn't help is a design review of the hw
<GitHub-m-labs>
[artiq] jordens commented on issue #1061: I suspect this particular issue is from a large number of packages (in our conda channels, previous builds on disk, or in conda-forge). Might not even be CPU bound. https://github.com/m-labs/artiq/issues/1061#issuecomment-400267477
<hartytp>
so maybe there will be some time to work on other things while that happens?
<sb0>
by "satisfactory" I mean stable and with inter-board sync
<sb0>
other things like rf switch and attenuator support also require drtio switching anyway
<hartytp>
sure
<sb0>
but, since (at the risk of sounding like I complain again) sayma has no shortage of obscure bugs, it's still quite open-ended
<hartytp>
once we get rid of these damn crashes etc, the rest of the work that needs to be done on Sayma doesn't look that bad
<sb0>
there's still plenty of inexplicable behavior: the other JESD clock not working, sequence errors not reported, the phase jumps
<GitHub134>
[smoltcp] dlrobertson opened pull request #250: Fix comment and collapse unneeded impl block (master...fix_ipv6option_nits) https://github.com/m-labs/smoltcp/pull/250
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<GitHub-m-labs>
[artiq] kesht123 commented on issue #1081: In gateware/rtio/sed/core.py, line 15, I changed the default ``enable_spread`` argument to ``False`` in the ``__init__`` of the ``SED`` class. I rebuilt the gateware and flashed it to the core device. Running the same script as above I see the same RTIO sequence errors https://github.com/m-labs/artiq/issues/1081#issuecomment-400300338
<GitHub-m-labs>
[artiq] gkasprow commented on issue #1065: 10R resistor serves another purpose. If one wants to stabilise the voltage at the FPGA terminals, R508 needs to be installed. Then this 10R would be shorted by trace resistance. This needs to be tested (stability) so I don't recommend touching this part at the moment. https://github.com/m-labs/artiq/issues/1065#issuecomment-400371870
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1065: > First, before any modification of VCCINT, please remove two big 0R resistors on the board bottom. This will disconnect the FPGA core from SMPS.... https://github.com/m-labs/artiq/issues/1065#issuecomment-400372589