<sb0>
hartytp, with the synchronization scheme I have in mind, sysref will have to meet s/h at the FPGA RTIO clock domain (same as JESD core). and the FPGA will confirm its s/h margin (like it does currently for sysref at the DAC since my last commit). does this qualify as "proper"?
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<sb0>
if we want to be paranoid, we can add a MultiReg anyway, but under normal conditions, all it will do is prevent metastability during the s/h scan
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<cr1901_modern>
Hmmm, the person asking for cygwin support kinda vanished after January. Still prob wouldn't hurt to clean up the patch as an example of how to add cygwin support to other backends.
<cr1901_modern>
rjo: Apologies in advance, but... I have a "todo" bullet for Migen that says "add toolchain tests". Are the platform tests (test_platform.py) we have now sufficient or were you looking for something more substantial?
<sb0>
oh, that's hilarious, the crash-kernel runs just fine on the DRTIO master when driving a remote SAWG on the satellite, and the DAC output looks fine
<sb0>
replace the MEMORY const with a regular stack-allocated array
<GitHub-m-labs>
[artiq] hartytp commented on issue #1065: @gkasprow @marmeladapk might also be worth double checking that we really have followed all Xilinx user guides on power supplies, decoupling, etc and that that decoupling capacitors have the correct voltage rating etc. https://github.com/m-labs/artiq/issues/1065#issuecomment-398666175
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1065: One workaround is to run the SAWG kernels over DRTIO. Both the Sayma DRTIO master and satellite seem surprisingly unaffected by the crashes, so far. If the master crashes it can in theory be replaced by Kasli. https://github.com/m-labs/artiq/issues/1065#issuecomment-398672104
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1065: One workaround is to run the SAWG kernels over DRTIO. Both the Sayma DRTIO master and satellite seem surprisingly unaffected by the crashes, so far. If the master crashes it can in theory be replaced by Kasli.... https://github.com/m-labs/artiq/issues/1065#issuecomment-398672104
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<GitHub-m-labs>
[artiq] hartytp commented on issue #1065: Note to self: one potentially significant difference between the DRIO and standalone Sayma builds is how the RTIO is clocked/reset. In standalone, the RTIO logic is clocked from the HMC7043 output and reset by the same signal that enables the clock input buffers: ... https://github.com/m-labs/artiq/issues/1065#issuecomment-398746747
<GitHub-m-labs>
[artiq] hartytp commented on issue #1065: Note to self: one potentially significant difference between the DRIO and standalone Sayma builds is how the RTIO is clocked/reset. In standalone, the RTIO logic is clocked from the HMC7043 output and reset by the same signal that enables the clock input buffers: ... https://github.com/m-labs/artiq/issues/1065#issuecomment-398746747
<GitHub-m-labs>
[artiq] hartytp commented on issue #1065: Note to self: one potentially significant difference between the DRIO and standalone Sayma builds is how the RTIO is clocked/reset. In standalone, the RTIO logic is clocked from the HMC7043 output and reset by the same signal that enables the clock input buffers: ... https://github.com/m-labs/artiq/issues/1065#issuecomment-398746747
<GitHub-m-labs>
[artiq] marmeladapk commented on issue #1065: @hartytp With boot:jump(0) sayma would do one full cycle from memtest to dac init, then reboot and hang on hmc7043 init. Now it always hangs on hmc830 lock.... https://github.com/m-labs/artiq/issues/1065#issuecomment-398772505
<GitHub-m-labs>
[artiq] marmeladapk commented on issue #1065: @hartytp With boot:jump(0) sayma would do one full cycle from memtest to dac init, then reboot and hang on hmc7043 init. Now it always hangs on hmc830 lock.... https://github.com/m-labs/artiq/issues/1065#issuecomment-398772505
<GitHub-m-labs>
[artiq] gkasprow commented on issue #1065: @sbourdeauducq do you use FPGA_DAC_SYSREF from HMC7043 to AMC FPGA? It has very low amplitude, roughly 200mV while other signals are 1V or more.... https://github.com/m-labs/artiq/issues/1065#issuecomment-398800516
<GitHub-m-labs>
[artiq] gkasprow commented on issue #1065: Can we set output of HMC7043 FPGA SYSREF to LVPECL? it is AC-terminated so it does not mater. At the moment it has two 200R to GND so the amplitude gets attenuated seriously. I'm worried about low amplitude. https://github.com/m-labs/artiq/issues/1065#issuecomment-398803751
<GitHub-m-labs>
[artiq] hartytp commented on issue #1065: @gkasprow Have you ever seen PRBS checks working with this board? Have you tested it with other versions of ARTIQ? Do you have another RTM you can try?... https://github.com/m-labs/artiq/issues/1065#issuecomment-398867930
<GitHub-m-labs>
[artiq] gkasprow commented on issue #1065: One of the board was perfectly working yesterday generating sinewave. The other board was tested and was working with PRBS some time ago. I tested all 10 boards with PRBS after I discovered issue with JESD termination. Now two of them has similar problems with PRBS and I'd love to understand why. https://github.com/m-labs/artiq/issues/1065#issuecomment-398909563