01:17 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1045: Enabling it will often cause experiments not to run due to underflows, so that's not very useful. https://github.com/m-labs/artiq/issues/1045#issuecomment-394127943

01:17 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1007: Any update? https://github.com/m-labs/artiq/issues/1007#issuecomment-394127964

02:46 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1043: FWIW, with 2018.1 I've run two different Sayma boards (after the various fixes bugs like SDRAM, HMC7043 noise, 1V8, etc.) continuously for days without any bug of this sort. https://github.com/m-labs/artiq/issues/1043#issuecomment-394130967

02:46 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1043: FWIW, with 2018.1 I've run two different Sayma boards (after the various fixes for bugs like SDRAM, HMC7043 noise, 1V8, etc.) continuously for days without any bug of this sort. https://github.com/m-labs/artiq/issues/1043#issuecomment-394130967

08:13 <GitHub-m-labs> [artiq] hartytp commented on issue #1026: @whitequark thanks for adding that. Do you want me to post a new UART trace with the memory dump? https://github.com/m-labs/artiq/issues/1026#issuecomment-394145241

08:14 <GitHub-m-labs> [artiq] hartytp commented on issue #1043: I'm using Vivado 2018.1 (current master doesn't meet timing on the 2017 version I was using), and see occasional illegal instructions on boot. https://github.com/m-labs/artiq/issues/1043#issuecomment-394145278

08:18 <GitHub-m-labs> [artiq] hartytp commented on issue #1045: I don't think that a debug mode with different (slower) timings to the "release" mode would be particularly useful.... https://github.com/m-labs/artiq/issues/1045#issuecomment-394145527

08:19 <GitHub-m-labs> [artiq] hartytp commented on issue #1045: I don't think that a debug mode with different (slower) timings to the "release" mode would be particularly useful.... https://github.com/m-labs/artiq/issues/1045#issuecomment-394145527

13:37 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1043: Yes, we need the memory dump,the rest of the crash message, and the corresponding ``runtime.elf``. https://github.com/m-labs/artiq/issues/1043#issuecomment-394162995

13:38 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1026: Yes, we need the memory dump, the rest of the crash message, and the corresponding ``runtime.elf``. https://github.com/m-labs/artiq/issues/1026#issuecomment-394163050

13:40 <GitHub6> [smoltcp] dlrobertson closed issue #213: Improve ChecksumCapabilities for a IPv4/IPv6 environment https://github.com/m-labs/smoltcp/issues/213

16:22 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #998: Some more data:... https://github.com/m-labs/artiq/issues/998#issuecomment-394173433

16:50 <GitHub-m-labs> [artiq] hartytp commented on issue #998: I do feel like there is something we're missing as there are a few odd bugs (crashes, dac glitches, etc) which don't make sense and don't seem very reproducible. Question is, if there is some common cause, how do we find it? More microscope probes? https://github.com/m-labs/artiq/issues/998#issuecomment-394175249

16:51 <sb0> wtf, vivado fails timing when you remove the jesd core

17:00 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #998: Bug is still present with the JESD core removed. Oddly, this makes Vivado fail timing in several places. https://github.com/m-labs/artiq/issues/998#issuecomment-394175798

18:27 <GitHub-m-labs> [artiq] hartytp commented on issue #998: Does removing the LOCs help? Can we remove those with appropriate timing constraints? https://github.com/m-labs/artiq/issues/998#issuecomment-394181431

20:04 <tpw_rules> sb0: hello?

20:08 <tpw_rules> i want to discuss the syntax changes i've made to fhdl with you and see if you would like to upstrema them

20:20 <GitHub-m-labs> [artiq] hartytp commented on issue #1043: > I'm using 2017.4. What version of Vivado are you using?? #910... https://github.com/m-labs/artiq/issues/1043#issuecomment-394188479

21:29 <hartytp> rjo: re suservo

21:30 <hartytp> I thought it might be worth adding a few final elements to the documentation of eem.SUServo to explain what the params do

21:30 <hartytp> the one I'm most interested in is t_rtt (e.g. reminding myself what the actual delay in Sampler is, etc)

21:30 <hartytp> I figured that it would be as quick to write a PR myself as to post an issue, so I did that https://github.com/hartytp/artiq/tree/suservo_docs

21:30 <hartytp> it's probably a bit verbose

21:31 <hartytp> can you have a quick skim over than and decide if you'd want a PR?

21:31 <hartytp> if you think it's just too verbose and nothing else is needed, then let me know