02:06 <GitHub65> [artiq] r-srinivas opened issue #638: Call method from getattr in kernel https://git.io/v1gIC

05:33 <GitHub18> [artiq] whitequark commented on issue #407: @r-srinivas Almost certainly independent one. https://git.io/v1gnU

05:57 <GitHub105> [artiq] whitequark commented on issue #638: `getattr` is not supported in kernels by design. Every use of `getattr` that could be in principle efficiently compiled can also be represented using closures, which also shows intent better IMO. Is there a reason you cannot rewrite what you want using closures? https://git.io/v1gcW

08:41 <sb0> whitequark, back?

10:05 <GitHub168> [artiq] sbourdeauducq commented on issue #570: I wouldn't be so fast. If PicoTCP turns out to be the only sensible way to fix those horrible network bugs, then we are stuck with the GPL. https://git.io/v1g6w

10:10 <GitHub27> [artiq] sbourdeauducq commented on issue #638: @whitequark He is not using ``getattr`` inside the kernel, and I don't see a technical reason for his use case not to be supported. https://git.io/v1gik

10:12 <GitHub81> [artiq] sbourdeauducq commented on issue #553: Basic gateware written, works in functional simulation. https://git.io/v1gir

10:12 <rjo> whitequark: yes. it's not complex. and it becomes compact and readable with migen.

10:13 <GitHub133> [artiq] sbourdeauducq commented on issue #627: @danielkienzlerNIST ping https://git.io/v1gi6

10:35 <GitHub129> [artiq] jordens commented on issue #570: It seems highly likely that either lwip is fixable or that the other to-be-released stack is suitable. https://git.io/v1g1U

14:38 <GitHub177> [artiq] jordens pushed 4 new commits to phaser2: https://git.io/v12Io

14:38 <GitHub177> artiq/phaser2 a629eb1 Robert Jordens: fir: add ParallelHBFCascade

14:38 <GitHub177> artiq/phaser2 d303225 Robert Jordens: fir: add ParallelFIR and test

14:38 <GitHub177> artiq/phaser2 7e0f3ed Robert Jordens: gateware/dsp: add FIR and test

14:45 <bb-m-labs> build #1154 of artiq is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1154

14:54 <GitHub109> [artiq] jordens pushed 3 new commits to phaser2: https://git.io/v12qZ

14:54 <GitHub109> artiq/phaser2 598da09 Robert Jordens: sawg: fix latency

14:54 <GitHub109> artiq/phaser2 f4ceace Robert Jordens: test/fir: needs mpl. don't run by default

14:54 <GitHub109> artiq/phaser2 efc9504 Robert Jordens: test/sawg: patch spline

15:09 <bb-m-labs> build #254 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/254

15:12 <bb-m-labs> build #1155 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1155

15:20 <GitHub66> [artiq] jordens pushed 1 new commit to phaser2: https://git.io/v123Y

15:20 <GitHub66> artiq/phaser2 18e3f58 Robert Jordens: sawg: reduce coefficient width

15:21 <bb-m-labs> build #255 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/255

15:24 <GitHub44> artiq/phaser2 ca636ef Robert Jordens: conda/phaser: build-depend on numpy

15:24 <GitHub44> [artiq] jordens pushed 1 new commit to phaser2: https://git.io/v12sL

15:47 <bb-m-labs> build #256 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/256

16:32 <GitHub66> [artiq] vontell opened issue #639: Determining if an edge was rise or fall from gate_both https://git.io/v12En

16:36 <GitHub171> [artiq] sbourdeauducq commented on issue #639: It's alternating rises and falls, so all you really need is the initial value. What do you need that for? https://git.io/v12EF

16:45 <bb-m-labs> build #257 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/257

19:53 <GitHub67> [artiq] vontell commented on issue #639: My current approach is also to use the initial value. However, how would I get this initial value; is there a TTLInOut method which would allow me to query the current input state of the channel? desired functionality is at issue [vontell/artiq-control#7](https://github.com/vontell/artiq-control/issues/7) https://git.io/v12hs

22:05 <GitHub24> [artiq] danielkienzlerNIST commented on issue #627: code:... https://git.io/v1a8a

22:31 <GitHub38> [artiq] jmizrahi commented on issue #615: @cr1901 I tried to test this today, but am having trouble because things seem to have moved around. I have been on misoc tag 0.3 and artiq branch release-2. I could not apply the misoc patch. I pulled the latest misoc master, and was then able to apply your patch, but artiq does not compile. Any way to fix this bug in a way that will let me stay on the release-2 branch for the time being? https://git.io

23:05 <cr1901_modern> Shit... better fix that