sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<whitequark>
sb0: do I understand correctly that the problem with building bios with clang-or1k is that it cannot handle l.mfspr/l.mtspr and 0-operand nop?
ylamarre has joined #m-labs
<rjo>
cr1901_modern: for migen/mibuild you have to weigh the trouble of having to manage two package (both for the developer as for the user) against bundling a few additional python modules in those cases where the mibuild tools can not be used (are there any?).
<cr1901_modern>
I DID say that I didn't promise my logic made sense :P
<cr1901_modern>
(well, sort of)
* cr1901_modern
is getting sick of his "e" key coming off his keyboard, and needs to stop holding off on buying replacement keycaps
<cr1901_modern>
http://t.co/eByd1LQqvN I assume this is limited to code edits where the edit doesn't change the side effects of code that has previously executed? Or maybe changes are "rolled back" if side effects change?
ylamarre has quit [Quit: ylamarre]
<whitequark>
jesus fuck libgcc is a mess
<whitequark>
so, libunwind and __gxx_personality_v0 are basically designed in lockstep
<whitequark>
since C++ is the major user of unwinding
<whitequark>
but the unwinder is a part of libgcc_s and __gxx_personality_v0 is a part of libstdc++
<whitequark>
so, LLVM has libunwind (with the unwinder) and libc++abi (with __gxx_personality_v0)
<whitequark>
and both of them have a DWARF parser.
<whitequark>
well, more like half of a DWARF parser.
<whitequark>
different half.
<whitequark>
and there's also the clang bits that generate the code, and LLVM bits for composing the typeinfo tables
<whitequark>
all of which are nominally independent and defined in standards but in practice are bug-compatible with gcc's implementation
<whitequark>
which is, needless to say, is godawful
<whitequark>
well, the good news is that the LLVM bits are actually very convenient to use, and libunwind itself is well, if under-, designed
<whitequark>
so the only thing i need to write is an __artiq_personality_v0
<cr1901_modern>
What's the v0 in the personality value again?
<whitequark>
version
<cr1901_modern>
Tthere's a personality_sj in the linked code. I've never seen that before, but I can tell what it means from the context. Figured there was a similar explanation for v*
<whitequark>
sjlj is just a horrible hack for iOS
<cr1901_modern>
Your sentence remains true if you remove the last two words :P
<sb0>
whitequark, there are problems like that yes, but I don't remember exactly
<sb0>
rjo, how exactly would you flatten the misoc namespace?
MiW has quit [Ping timeout: 256 seconds]
MiW has joined #m-labs
<GitHub94>
[migen] enjoy-digital pushed 2 new commits to master: http://git.io/vYWo5
<GitHub94>
migen/master 1f1ff5a Florent Kermarrec: migen/fhdl/tools: fix rename_clock_domain when new == old...
<GitHub6>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/vYW7a
<GitHub6>
misoc/master 0a115f6 Florent Kermarrec: litepcie/frontend/dma: group loop index and count in loop_status register (avoid 2 register reads)
<GitHub54>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/vYWbN
<GitHub54>
misoc/master b75b93d Florent Kermarrec: misoclib/com/uart: replace revered Migen FIFO function with specific _get_uart_fifo function for our use case.
ylamarre has quit [Quit: ylamarre]
<mithro>
Does misoc have a logo? Or is it just migen?
<sb0>
it has no logo yet, but you can use the migen one i guess
<mithro>
sb0: so what is the story with _connectors in mibuild?
<sb0>
have you seen the fmc examples in artiq?
<sb0>
eg gateware/nist_qc2.py
<sb0>
rjo, have you noticed that pygtgraph has a "GradientWidget" that does some of the things of your proposed fancy scan widget?
<cr1901_modern>
mithro: See mercury in mibuild for another example (a lot of the I/O that is exposed as connectors has a dual purpose; I provide some defaults like LEDs)
<mithro>
cr1901_modern / sb0: yeah I was taking a peak at them. I wondered if there was any more extra structure was planned in the future, or if the idea was to keep it pretty light?
<mithro>
gah, I hate writing PR :(
<sb0>
mithro, the general idea in migen/misoc is to keep everything pretty light unless absolutely needed
<mithro>
sb0: I was thinking if there was a few extra light classes around connectors it could help with the ability to tag things with more information / documentation - IE This is compatible with standard X version Y, or this connector compatible with 3.3 and 2.5 voltage levels
<whitequark>
sb0: what'd qc2 mean?
<sb0>
quantum computing 2 (i think)
<whitequark>
sb0: ok, so, question about EH
<whitequark>
what kinds of data do we want to record within an APython exception?
<whitequark>
well, there's obviously the typeinfo entry, which in our case is just a string
<sb0>
the exception type_
<sb0>
?
<sb0>
the current code uses integers for that and is fine. why go through the complication of strings?
<sb0>
this thing has to work completely by September ...
<whitequark>
complication? strings are simpler
<whitequark>
well, it doesn't really matter what in particular lies inside the typeinfo entry, only its address is needed
<sb0>
well then the runtime has to pass the exception ID to the host
<sb0>
and strings are a bit harder to encode than ints. again, not a blocker, but it all adds up
<whitequark>
ok, I'll look at that
<whitequark>
but what I was really asking is associated information
<sb0>
could you make a simple prototype that talks to the board and then add stuff on top of that?
<sb0>
as for the associated info, it's just a couple 64-bit ints at most
<cr1901_modern>
it's an XDG Menu spec parser. One of the XML nodes that can be parsed is <Include>, which is a set of boolean ops.
<cr1901_modern>
<And> <Or> <Not>, etc
<cr1901_modern>
One of the "ops" to be parsed is <Category>, which attempts to match a string, and it use ast.Load()
<cr1901_modern>
And b/c of course it doesn't work right, I'm stuck debugging it
<cr1901_modern>
... oh holy shit that's gross... it's creating python statements on the fly that depend on the variable having a certain name o.0;
nickjohnson has joined #m-labs
<nickjohnson>
Hi, I'm looking at migen, and struggling to find any examples of how you instantiate and connect signals to one module from another - particularly how you hook up the clocks
<nickjohnson>
Can anyone point to an example for me?
<rjo>
nickjohnson: clocks are done through clock domains. they become visible globally "by name". signals are done by accessing other modules' attributes.
<nickjohnson>
rjo: is there any way to have a clock that's local to a module?
<rjo>
but that is all covered in the docs! do you have something specific?
<nickjohnson>
An example of one module using another would be good
<nickjohnson>
In this case what I want to do is invoke a module and connect its clock to a general purpose signal in the module that's instantiating it
<rjo>
have the parent module create and drive the clock domain, and then the child module can just use it.
<rjo>
more exampes for that are in misoc, the various CRGs for the platforms.
<whitequark>
grrrr, incomplete llvmlite bindings
<cr1901_modern>
Just spent two hours debugging that damn XDG library because I didn't read the XDG specs close enough... yay! :/
antgreen has joined #m-labs
<whitequark>
hm, I'm like 90% sure the switch instruction in llvmlite never has worked
<whitequark>
oh, misread
_florent_ has joined #m-labs
<GitHub88>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/vYBuL
<_florent_>
rjo: I already tried to clean it up, but maybe you have some others ideas.
<_florent_>
I don't think there are still things to share between cores and I don't clearly see how you want to flatten things.
<_florent_>
Can you eventually prepare something so that we can discuss the pros/cons vs the actual arborescence?
<whitequark>
"arborescence" hah
<_florent_>
sorry french word :) --> the actual misoc files/directories organization
ylamarre has quit [Quit: ylamarre]
<whitequark>
no, that's actually a very good word
<whitequark>
I'll make use of it.
<rjo>
_florent_: ok, if we do this in a misoc issue?
<_florent_>
yes np
<whitequark>
sb0: would you fork llvmlite into m-labs org? the upstream is unresponsive
<GitHub150>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/vYRI9
<GitHub150>
misoc/master 4c601cc Florent Kermarrec: misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq....
<GitHub130>
[misoc] enjoy-digital force-pushed master from 4c601cc to 8d1c555: http://git.io/LjONPA
<GitHub130>
misoc/master 8d1c555 Florent Kermarrec: misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq....