sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<rjo> ysionneau, sb0_: if have added support to openocd to support out boards (all of xilinx should work afaict) well. with a much simpler bscan_spi proxy bitstream. if we package something it should not be xc3sprog/fpgaprog if at all possible
ylamarre has quit [Remote host closed the connection]
ylamarre has joined #m-labs
attie has quit [Ping timeout: 265 seconds]
<GitHub10> [artiq] jordens pushed 1 new commit to master: http://git.io/vqYHP
<GitHub10> artiq/master 380f498 Robert Jordens: Merge branch 'namespace_all'...
<GitHub6> [artiq] jordens deleted namespace_all at 2674ed1: http://git.io/vqYHX
attie has joined #m-labs
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#282 (master - 380f498 : Robert Jordens): The build has errored.
travis-ci has left #m-labs [#m-labs]
_whitelogger has quit [Ping timeout: 252 seconds]
_whitelogger has joined #m-labs
<GitHub124> [artiq] jordens pushed 1 new commit to master: http://git.io/vqYjD
<GitHub124> artiq/master 959ba99 Robert Jordens: pipistrello: try simpler constraints
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#283 (master - 6faa8ec : Robert Jordens): The build has errored.
travis-ci has left #m-labs [#m-labs]
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#284 (master - 959ba99 : Robert Jordens): The build passed.
travis-ci has left #m-labs [#m-labs]
<GitHub193> [artiq] jordens pushed 1 new commit to master: http://git.io/vqOfl
<GitHub193> artiq/master 409c66e Robert Jordens: test: convert lda/tcube/409b to hardware_testbench
<GitHub174> [artiq] jordens pushed 2 new commits to master: http://git.io/vqOTo
<GitHub174> artiq/master f6e8537 Robert Jordens: travis: add email-notification for hardware-ci
<GitHub174> artiq/master e056438 Robert Jordens: travis: remove gitter webhook
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#285 (master - 409c66e : Robert Jordens): The build passed.
travis-ci has left #m-labs [#m-labs]
ylamarre has quit [Remote host closed the connection]
ylamarre has joined #m-labs
<GitHub197> [artiq] jordens pushed 1 new commit to master: http://git.io/vqOkF
<GitHub197> artiq/master a3fe538 Robert Jordens: test: fix get_from_ddb
ylamarre has quit [Remote host closed the connection]
ylamarre has joined #m-labs
ylamarre has quit [Client Quit]
<GitHub83> [artiq] jordens pushed 1 new commit to master: http://git.io/vqOIy
<GitHub83> artiq/master 096c722 Robert Jordens: travis: shut up conda and binstar progress bars
<GitHub16> [artiq] jordens pushed 1 new commit to master: http://git.io/vqOLJ
<GitHub16> artiq/master fbdc050 Robert Jordens: travis: logout of binstar after upload
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#286 (master - e056438 : Robert Jordens): The build has errored.
travis-ci has left #m-labs [#m-labs]
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#288 (master - 096c722 : Robert Jordens): The build passed.
travis-ci has left #m-labs [#m-labs]
<GitHub52> [artiq] jordens pushed 1 new commit to master: http://git.io/vqOqG
<GitHub52> artiq/master 19442ef Robert Jordens: travis: binstar takes -q before command...
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#289 (master - fbdc050 : Robert Jordens): The build passed.
travis-ci has left #m-labs [#m-labs]
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#287 (master - a3fe538 : Robert Jordens): The build has errored.
travis-ci has left #m-labs [#m-labs]
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#290 (master - 19442ef : Robert Jordens): The build passed.
travis-ci has left #m-labs [#m-labs]
<rjo> yay. let's see how fragile this is: artiq ci unittests with hardware logs end up at: http://people.phys.ethz.ch/~robertjo/artiq-ci/
_whitelogger has quit [Ping timeout: 252 seconds]
_whitelogger has joined #m-labs
<mithro> Evening everyone!
<sb0_> hi mithro
<sb0_> " for strings (again)
<whitequark> you really do not get tired correcting that...
<sb0_> yes, I should write a bot I guess
<sb0_> mithro, if not cfg_bypass -> if cfg_bypass
<mithro> sb0_: yeah - a precommit script would save you having to correct that over and over
<sb0_> mithro, also I don't think the cfg_bypass stuff has anything to do with the cable
<sb0_> """\ -> """
<mithro> sb0_: I don't really understand why/what the cfg stuff is doing
<sb0_> it's just defining the configuration instruction encodings for the FPGA you are using
<sb0_> for some reason, urjtag doesn't include them
<mithro> sb0_: so - maybe that should come from the urjtag version?
travis-ci has joined #m-labs
<travis-ci> mithro/migen#38 (master - 0df9c16 : Tim 'mithro' Ansell): The build passed.
travis-ci has left #m-labs [#m-labs]
<sb0_> mithro, you need them for your board but they weren't included for m1, is that right?
<mithro> sb0_: from what I found in the #milkymist IRC logs was a bit confusing
<sb0_> mithro, you should fix urjtag so that they aren't needed for your FPGA
<sb0_> note that different FPGAs use different encodings, so you can't just copy and paste the m1 commands
<GitHub63> [migen] sbourdeauducq pushed 2 new commits to master: http://git.io/vqOgR
<GitHub63> migen/master 1d1f851 Tim 'mithro' Ansell: Allow using non-milkymist cables with UrJTAG.
<GitHub63> migen/master 73ea404 Sebastien Bourdeauducq: Merge branch 'master' of https://github.com/m-labs/migen
<sb0_> and yeah, urjtag giving up on unknown steppings is annoying as well
travis-ci has joined #m-labs
<travis-ci> m-labs/migen#53 (master - 73ea404 : Sebastien Bourdeauducq): The build passed.
travis-ci has left #m-labs [#m-labs]
travis-ci has joined #m-labs
<travis-ci> mithro/migen#39 (master - 73ea404 : Sebastien Bourdeauducq): The build passed.
travis-ci has left #m-labs [#m-labs]
travis-ci has joined #m-labs
<travis-ci> mithro/migen#40 (urjtag - e2683e9 : Tim 'mithro' Ansell): The build passed.
travis-ci has left #m-labs [#m-labs]
travis-ci has joined #m-labs
<travis-ci> mithro/migen#41 (urjtag - 8b65ef9 : Tim 'mithro' Ansell): The build passed.
travis-ci has left #m-labs [#m-labs]
mumptai has joined #m-labs
<sb0_> mithro, this is a urjtag problem, not a migen problem
<mithro> sb0_: the other option is to force users of migen+urjtag set up a .jtag/rc file?
fengling has joined #m-labs
nicksydney_ has quit [Remote host closed the connection]
mumptai has quit [Quit: Verlassend]
nicksydney has joined #m-labs
<GitHub62> [misoc] enjoy-digital pushed 2 new commits to master: http://git.io/vqO9o
<GitHub62> misoc/master 23541b5 Florent Kermarrec: software/bios: call eth_mode only if we have an ethernet mac (we don't need to call it when we have a hardware UDP/IP stack)
<GitHub62> misoc/master c1ca928 Florent Kermarrec: liteeth: small logic optimizations on mac (eases timings on spartan6)
sb0__ has joined #m-labs
sb0_ has quit [Ping timeout: 252 seconds]
fengling has quit [Ping timeout: 246 seconds]
fengling has joined #m-labs
_florent_ has joined #m-labs
fengling has quit [Ping timeout: 256 seconds]
nicksydney has quit [Quit: No Ping reply in 180 seconds.]
sb0 has joined #m-labs
sb0__ has quit [Read error: Connection reset by peer]
<mithro> sb0: Do you have any thoughts around a generic self describing debug bus for misoc - IE A low cost way for different cores to expose things like counters / states / etc and description of those elements? (Does misoc already have something like that?)
<sb0> there's miscope
<sb0> but I have't looked much at it yet
<mithro> What's miscope?
<mithro> litescope is more about being a lower-level logic analyzer right?
<mithro> I was thinking more like it would be awesome if the dvi-sampler exported information about like vsync/hsync interval and jitter
<mithro> or other kind of stats/counters/etc
<_florent_> you can probably create CSR registers for that
<mithro> What are CSR registers?
<_florent_> the registers we are using in migen/misoc
<_florent_> ex:https://github.com/m-labs/misoc/blob/a8b9c126cdcb7bee6ecf6a46bcdc3c06ec366f5c/misoclib/cpu/identifier.py#L13
<mithro> What does CSR stand for? Control/Status Register ?
<_florent_> yes (unless sb0 has another meaning for it)
<mithro> I was wonder how expensive it might be if you added CSR registers for things which wouldn't normally be directly connected to the bus?
<mithro> what is Compiler-RT used in misoc for?
<_florent_> it depends how many registers you want to add. But otherwise from where do you want to access to the information generated by the cores?
<mithro> _florent_: I would want to access it from a CPU - but I wasn't sure if a large parallel bus would be more expensive than a serial bus in terms of interconnect overhead?
<mithro> oh - it looks like someone has already invented CSR-2 bus?
<_florent_> yes that's what we are using (CSR was 32bits IIRC)
<mithro> _florent_ / sb0: is there a good resource to understand LASMIcon apart from http://m-labs.hk/migen-slides.pdf ?
<_florent_> http://m-labs.hk/migen.pdf has some informations about LASMI
key2 has joined #m-labs
balrog has quit [Excess Flood]
balrog has joined #m-labs
tija has joined #m-labs
<sb0> ysionneau, can't the pxi6733 driver take a multidimensional array instead of the concatenation of the channel data?
<ysionneau> as long as the driver transforms the multidimensional array into an unidimensional one I guess yes it's doable
<ysionneau> I guess you're right that would be a better API
<ysionneau> more high level at least
Gurty has quit [Remote host closed the connection]
<sb0> why does CreateAOVoltageChan expect min/max values?
<sb0> and is the unit volts?
<sb0> for the samples
<ysionneau> yes unit is Volt
<ysionneau> I don't know exactly why you need to specify the min/max value :/
<sb0> will there be a bug?
<ysionneau> if the min / max value is wrong?
<ysionneau> I honestly don't know
<ysionneau> the documentation doesn't say much about what the min/max are for
<ysionneau> " The minimum value, in units, that you expect to generate."
* ysionneau is googling a bit more
<ysionneau> I see some forum threads saying the min/max is useful for Analog *input* to select one of different input range to best fit the expected input values
<ysionneau> but for output ... maybe there are several output stages for different voltage ranges, dunno
<sb0> why does the daqmx also need to know about the sample rate?
<sb0> is it setting up some aliasing filter?
<sb0> will bad things happen if the clock is stopped?
<ysionneau> what is sure (because we tested) is that if the clock frequency does not match the sample rate, weird stuff can happen
<ysionneau> for instance the device stopping before the end of the sample list
<ysionneau> at first I hard coded a 1 KHz sample rate, and Katie was feeding in a 100 kHz clock, and the device stopped after a few samples
<ysionneau> providing the correct sample rate fixed that
<sb0> and what happens if you pause the clock?
<ysionneau> I don't think Katie tested that
<sb0> well, that's what some people recommended me to do ...
<sb0> hpefully that will work
<GitHub32> [artiq] sbourdeauducq pushed 4 new commits to master: http://git.io/vqsmz
<GitHub32> artiq/master 2eeaa3b Sebastien Bourdeauducq: pxi6733: clean up docstring
<GitHub32> artiq/master 58c0150 Sebastien Bourdeauducq: ttl: improve clockgen doc
<GitHub32> artiq/master 2bc8286 Sebastien Bourdeauducq: pdq2/mediator: fix arm
<ysionneau> the API description says
<ysionneau> The sampling rate in samples per second per channel. If you use an external source for the Sample Clock, set this value to the maximum expected rate of that clock.
<sb0> oh, ok, so that probably should be fine
<sb0> this pxi device looks weird
<ysionneau> yes
Gurty has joined #m-labs
travis-ci has joined #m-labs
<travis-ci> m-labs/artiq#291 (master - f9d8781 : Sebastien Bourdeauducq): The build passed.
travis-ci has left #m-labs [#m-labs]
ylamarre has joined #m-labs
cr1901_modern has quit [Quit: Leaving.]
nicksydney has joined #m-labs
tariq786 has joined #m-labs
<tariq786> www.antaresmicro.com for ASIC /FPGA design services
<ysionneau> hello, looks like spam :)
key2 has quit [Ping timeout: 255 seconds]
tija has quit [Quit: Connection closed for inactivity]
<whitequark> "Take a look at some of our past projects including this one for Google Summer of Code 2014.
<whitequark> (empty page)
<whitequark> oh, it's a link that is not underlined and the same color as the text. wow
<ysionneau> yeah it's just a link
<ysionneau> yes :p
<tariq786> no spam
<tariq786> ysionneau: Nothing spam. All original work
<ysionneau> I mean, just joining an IRC channel, no "hello" and a link to your own private company website, looks like spam behaviour :p
<ysionneau> are you using Migen for your project?
<tariq786> not yet
<tariq786> Its already done in Verilog
<tariq786> Do you have some project in mind that you want to get done in Migen
<whitequark> why are you using colored text, it is distracting
<tariq786> I heard a lot about migen and want to use it. Just looking for some good project
<tariq786> here you go without color :)
<tariq786> sorry it is http://eda-playground.com
<ysionneau> or just edaplayground.com , we know about this website, it by the way supports Migen simulation :)
<tariq786> Anyway, this is just to hi to you all and appreciate your work on Migen
<tariq786> yes. I saw it. Very nice work done by you guys
<tariq786> i hope i can be of some help
<ysionneau> well, don't hesitate to stand by on this channel, look at the conversations, use Migen, report bugs, add the features that you like
<ysionneau> add support for your board for instance, this sort of things
<ysionneau> you can submit issues on github, and send patches to the mailing list (no pull request)
<tariq786> yup. I am aware on all of this
<sb0> hi tariq786 , welcome
<tariq786> sbo: My pleasure. Thanks very much. Glad to be with right minded people
<tariq786> If there are some example projects that you want to do, please let me know where i could find their list
_whitelogger has joined #m-labs
sb0 has quit [Ping timeout: 255 seconds]
<rjo> ysionneau: lda/hidapi looks like it breaks intermittently and then has some queuing mixup. any ideas? http://people.phys.ethz.ch/~robertjo/artiq-ci/artiq-ci_20150705114415-nist_rj1-5db52b1_newassy.log
<ysionneau> rjo: are those tests running with real hw?
<ysionneau> ah it seems so
<ysionneau> I'll have a look tomorrow morning
<ysionneau> I guess you can open an issue with the first failing test with the Hid exception
<rjo> yes.
<rjo> i suspect there are two issues (the error and the queuing mess-up) and both are in hiapi.
<GitHub63> [misoc] enjoy-digital pushed 2 new commits to master: http://git.io/vqGCF
<GitHub63> misoc/master e011f93 Florent Kermarrec: use sets for leave_out
<GitHub63> misoc/master c100ef6 Florent Kermarrec: liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage with MII phy)
ylamarre has quit [Ping timeout: 248 seconds]