sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
ylamarre has joined #m-labs
ylamarre has quit [Read error: No route to host]
ylamarre1 has joined #m-labs
ylamarre1 has quit [Quit: ylamarre1]
<rjo> sb0__: how is an asynchronous FIFO supposed to behave if just one clock domain resets? doesn't that lead to invalid data showing up and/or valid data being overwritten?
<sb0__> is that with the latest runtime?
<sb0__> yes, you should reset both domains
<rjo> i guess driving both resets (with MultiReg on one) with either the and or the or of the two clockdomain resets dependeing on the preferred behavior.
<rjo> that is always with the current bitstream+bios+runtime.
<rjo> and the toolchain from conda.
<rjo> would somebody be willing to do a bit of code review to push the patches through openocd: http://openocd.zylin.com/#/q/owner:jordens%2540gmail.com+status:open
<sb0__> MultiReg may miss some reset pulses. you should use AsyncResetSynchronizer
<rjo> ack
aeris has quit [Quit: en a pas]
aeris has joined #m-labs
rjo has quit [Quit: Lost terminal]
rjo has joined #m-labs
nicksydney has quit [Remote host closed the connection]
nicksydney has joined #m-labs
<sb0__> whitequark, can you have a quick look at the constant string support in RPCs?
<sb0__> I'm going to factor in the new RDB/PDB API soon, and it'll break without that
<whitequark> sb0__: sure
<whitequark> can you elaborate? I've never touched RPCs so far
<sb0__> except that the goal is to remove all string literals from RPC calls
<whitequark> why do you want to remove string literals from RPC calls?
<sb0__> so we can support things like self.set_result("result_name", value) in kernels
<sb0__> even though the compiler does not support strings
<whitequark> it would be easier to add strings to the compiler
<sb0__> so you'd replace set_result with a closure that contains result_name
<sb0__> no, it would not
<whitequark> huh? just adding support for literals is like ten lines of code
<whitequark> without adding any methods or anything
<sb0__> you need to support that in the runtime as well, get it transmitted over the RPC protocol
<sb0__> the linker need to process the string relocations
<sb0__> all those details are a lot more than 10 lines of code, sorry
<whitequark> 'string relocations'?
<sb0__> yes, where are you going to store the literal?
<whitequark> rodata
<sb0__> yes. and the linker doesn't support rodata relocations right now.
<whitequark> ah.
<whitequark> ok
<whitequark> so how would the closure look like?
<whitequark> in essence, you're creating a new RPC call for every combination of strings, right?
<sb0__> yes
<sb0__> which is totally fine for the purpose of accessing certain results/parameters
<whitequark> that makes sense
<whitequark> sure. that can be done. I'd rather do it at codegen time though
<sb0__> maybe, but when would that work, i.e. the current unit tests can be rewritten to use set_result("xxx",...) and function properly on the device?
sb0_ has joined #m-labs
<whitequark> the unit tests currently go through LLVM anyway
<whitequark> so, yes
sb0__ has quit [Ping timeout: 264 seconds]
<sb0_> my question was more: if you want to implement that in your new codegen compiler (only), will it work sometime next week?
<whitequark> I think so. SSA IR should be done by tomorrow already
<whitequark> pipistrello tracking # not updated since 29th...
ylamarre has joined #m-labs
sb0_ has quit [Quit: Leaving]
<cr1901_modern> seeedstudio took a month to ship me my CPLD board (which doesn't even fit on a breadboard properly), and they didn't update the status of it at any time...
sb0 has joined #m-labs
<GitHub120> [artiq] whitequark pushed 5 new commits to new-py2llvm: http://git.io/vqA3V
<GitHub120> artiq/new-py2llvm 4358c5c whitequark: Unbreak return type inference.
<GitHub120> artiq/new-py2llvm 16432d2 whitequark: Implement escape analysis.
<GitHub120> artiq/new-py2llvm 4785f0a whitequark: Don't error out in inferencer if builtin arguments have polymorphic types.
<whitequark> whoa, I haven't pushed in a while
<sb0> so you're doing the whole IR thing?
<sb0> the flow would be AST -> IR -> transforms (interleave, inline, etc.) -> LLVM -> machine code?
<whitequark> yes. inlining and interleaving the ASTs is insane
<sb0> what's wrong with it?
<sb0> you can unparse nicely
<whitequark> you've encountered the problems with inlining yourself, haven't you?
<sb0> that can be solved by adding goto
<whitequark> it simply doesn't compose
<whitequark> note that I'm not converting *everything* to an IR, expressions stay
<whitequark> it's mostly a representation for control flow
<whitequark> with AST inlining, you'd be doing the exact same thing, but in an error-prone ad-hoc way
<sb0> is there a nice way to dump it for debugging?
<whitequark> str(fn)
<whitequark> well, not quite all code for that is in place, locations're missing
<whitequark> but I expect it to be readable
<whitequark> the SSA conversion here mainly involves lowering control flow and lexical scoping, both of which cause trouble when inlining and interleaving...
<cr1901_modern> whitequark: https://twitter.com/whitequark/status/619932160338849793 You think this is the network effect biting us on the ass?
sb0_ has joined #m-labs
sb0 has quit [Ping timeout: 250 seconds]
sb0_ has quit [Ping timeout: 255 seconds]
sb0_ has joined #m-labs