lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub39> [misoc] sbourdeauducq pushed 132 new commits to master: http://git.io/Abgz
<GitHub39> misoc/master a160b04 Florent Kermarrec: init repo
<GitHub39> misoc/master 0826811 Florent Kermarrec: etherbone: import core from Robert Jordens
<GitHub39> misoc/master 46c4841 Florent Kermarrec: mac: import files from MiSoC
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<jwbritto> Yann, Any luck with the KC705 board file?
<ysionneau> jwbritto: hi, Joe, I just sent you some patches
<ysionneau> sorry for the delay
<jwbritto> Got it. :)
<ysionneau> I'm trying to synthesize it right, now, but it takes something like 10 minutes to do it
<ysionneau> and so far I didn't manage to get it working
<ysionneau> I hope you will find the issue
<ysionneau> jwbritto: ok now the Placer accepts to use a non clock-dedicated pin, let's see if it goes all the way to bitstream generation
<ysionneau> placement done, going through routing...
<ysionneau> routing done
<ysionneau> humm it fails during "write_bitstream" almost there !
<ysionneau> jwbritto: here is the error I get : http://pastebin.com/t3Ltr7CB
<ysionneau> ah there is an issue with the pin location generation, it ends up putting
<ysionneau> set_property LOC LA07_N [get_ports dds_d[6]]
<ysionneau> LA07_N instead of the real ball name of the fpga
<ysionneau> issue comes from there return "set_property LOC " + c.identifiers[0] (mibuild/xilinx_vivado.py)
<ysionneau> jwbritto: still reading me?
<ysionneau> jwbritto just sent you something to fix by email
<ysionneau> I forgot to put "LPC:" in front of both LA07_N and LA17_CC_N line 40 of artiq_kc705.py
* ysionneau restarts synthesis and prays
<jwbritto> OK.
<jwbritto> We're trying this now.
<ysionneau> ok, I'm also trying at the same time
<ysionneau> but this Vivado tool takes forever to process
<jwbritto> We found the same problem with Vivado. SB is switching back to ISE.
<jwbritto> Which he says compiles far faster.
<ysionneau> oh, but ISE can synthesize for Kintex 7 of KC705??
<ysionneau> (yes it does compile faster)
<ysionneau> jwbritto: when you say, in your email, that you applied the patches, did you also add the missing "LPC:" ?
<jwbritto> Yes.
<ysionneau> ok good
<ysionneau> jwbritto synthesis just finished here with Vivado, I have a bitstream file. Do you want me to send it to you?
<ysionneau> in case you want it, here it is: http://sionneau.net/artiq/binaries/kc705/artiqminisoc-kc705.bit
<ysionneau> jwbritto: does it provide a working SoC with access to FMC I/O?
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<ysionneau> heading to bed now, good luck with the board testing jwbritto !