lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub26> [artiq] sbourdeauducq pushed 3 new commits to master: http://git.io/ApEA
<GitHub26> artiq/master 9485372 Yann Sionneau: units: add support for abs() on Quantity
<GitHub26> artiq/master 1b59442 Yann Sionneau: units: add support for V (Volt)
<GitHub26> artiq/master d51493f Sebastien Bourdeauducq: language/core: fix interpreter implementations of time/cycle conversions
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<travis-ci> m-labs/artiq#31 (master - d51493f : Sebastien Bourdeauducq): The build passed.
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<GitHub116> [misoc] enjoy-digital pushed 3 new commits to master: http://git.io/AhCZ
<GitHub116> misoc/master 60effe1 Florent Kermarrec: move files to liteeeth and create example_designs directory
<GitHub116> misoc/master 00862a3 Florent Kermarrec: liteeth: fix import (from liteeth --> from misoclib.liteeth)
<GitHub116> misoc/master 02b3f51 Florent Kermarrec: liteeth: fix example_designs generation
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<GitHub146> [migen] enjoy-digital pushed 3 new commits to master: http://git.io/AjLT
<GitHub146> migen/master b3faf5f Florent Kermarrec: mibuild: better file organization (create directory for each vendor and move programmers in it)
<GitHub146> migen/master e27a94e Florent Kermarrec: mibuild: add VivadoProgrammer (only load_bitstream)
<GitHub146> migen/master bd5ed09 Florent Kermarrec: platforms: add default_clk_freq/default_clk_name (to use it on simple designs to test MiSOC on various platforms)
<GitHub71> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/AjLY
<GitHub71> misoc/master 554731a Florent Kermarrec: targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period)
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<GitHub195> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/Aj8Z
<GitHub195> migen/master e6a21b2 Florent Kermarrec: mibuild: fix missing xilinx_common -->xilinx.common change
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<GitHub54> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/xvJL
<GitHub54> artiq/master b672a99 Yann Sionneau: lda: add support for ping
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<travis-ci> m-labs/artiq#32 (master - b672a99 : Yann Sionneau): The build passed.
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<GitHub159> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/xv9B
<GitHub159> migen/master 8da1faf Florent Kermarrec: mibuild: move identifier to platforms
<GitHub69> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/xv9N
<GitHub69> misoc/master 310e6e7 Florent Kermarrec: gensoc: get platform_id from platform
<ysionneau> _florent_: I think you left a print in this commit
<_florent_> ah yes... thanks!
<ysionneau> np :)
<GitHub198> [misoc] enjoy-digital force-pushed master from 310e6e7 to 5ac5ffe: http://git.io/LjONPA
<GitHub198> misoc/master 5ac5ffe Florent Kermarrec: gensoc: get platform_id from platform
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<jboulder> Yann....
<jboulder> Joe in Boulder.
<ysionneau> jboulder yes ?
<ysionneau> hi !
<jboulder> I'm rebuilding the Xilinx environment to compile for the KC705.
<jboulder> SB and I found that the Vivado environment was very slow due to some sort of a bug.
<jboulder> So, I've installed the full ISE per SB's suggestion.
<ysionneau> I can confirm it's slow as hell on my computer as well
<jboulder> However it looks like the misoc build tools rely on Vivado.
<ysionneau> ok, I didn't know ISE supported Kintex 7, but if SB says so it must :)
<jboulder> rabi@vboxartiq:~/artiq-dev/misoc$ ./make.py -X ~/artiq-dev/artiq/soc -t artiq_kc705 all
<jboulder> Is what I type.
<ysionneau> ok
<jboulder> make: Leaving directory `/home/rabi/artiq-dev/misoc/software/bios'
<jboulder> Traceback (most recent call last):
<jboulder> File "./make.py", line 185, in <module>
<jboulder> vns = platform.build(soc, build_name=build_name, **build_kwargs)
<jboulder> File "/home/rabi/artiq-dev/migen/mibuild/xilinx_vivado.py", line 114, in build
<jboulder> _run_vivado(build_name, vivado_path, source)
<jboulder> File "/home/rabi/artiq-dev/migen/mibuild/xilinx_vivado.py", line 81, in _run_vivado
<jboulder> settings = xilinx_common.settings(vivado_path, ver)
<jboulder> File "/home/rabi/artiq-dev/migen/mibuild/xilinx_common.py", line 12, in settings
<jboulder> vers = list(tools.versions(path))
<jboulder> File "/home/rabi/artiq-dev/migen/mibuild/tools.py", line 30, in versions
<jboulder> for n in os.listdir(path):
<jboulder> FileNotFoundError: [Errno 2] No such file or directory: '/opt/Xilinx/Vivado'
<jboulder> Is the error....
<jboulder> It looks like the build script looks for Vivado and not ISE.
<ysionneau> 2 sec
<jboulder> OK
<ysionneau> try to add -Op toolchain ise in your command line
<ysionneau> ./make.py -X ~/artiq-dev/artiq/soc -t artiq_kc705 -Op toolchain ise all
<jboulder> Brilliant! It's now moving forward with the compile.
<ysionneau> :)
<ysionneau> cool
<jboulder> Fingers crossed. Your configuration for the adapter board is in the build. Will let you know how it goes.
<ysionneau> were you able to use the bitstream I sent?
<jboulder> No. There was something the SB added to the source -- I don't recall what exactly.
<jboulder> One or more errors were found during NGDBUILD. No NGD file will be written.
<jboulder> Writing NGDBUILD log file "artiqminisoc-kc705.bld"...
<jboulder> Traceback (most recent call last):
<jboulder> File "./make.py", line 185, in <module>
<jboulder> vns = platform.build(soc, build_name=build_name, **build_kwargs)
<jboulder> File "/home/rabi/artiq-dev/migen/mibuild/xilinx_ise.py", line 174, in build
<jboulder> self.map_opt, self.par_opt)
<jboulder> File "/home/rabi/artiq-dev/migen/mibuild/xilinx_ise.py", line 120, in _run_ise
<jboulder> raise OSError("Subprocess failed")
<jboulder> OSError: Subprocess failed
<jboulder> Is new error...
<ysionneau> it just failed?
<ysionneau> Could you paste to pastebin.com the entire synthesis logs?
<jboulder> Yes...
<ysionneau> I think I know what's going on, I've put some constraint in the target file using "Vivado" syntax instead of ISE syntax
<ysionneau> that could be the issue
<ysionneau> to allow synthesis to proceed with a non clock dedicated pin
<jboulder> I've pasted what's in the buffer of my terminal. I'll repeat the build process with the output to file so I can paste a full transcript.
<ysionneau> yeah ok syntax error, that's it
<ysionneau> don't do this
<ysionneau> I already have the issue
<GitHub129> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/xfBE
<GitHub129> misoc/master 5e8a0c4 Florent Kermarrec: gensoc: add mem_map and mem_decoder to avoid duplications
<ysionneau> let me find the syntax for ISE ...
<jboulder> OK
<_florent_> hi jboulder
<_florent_> I can send you a patch to speed up vivado if you want
<_florent_> with this patch it does not take more than 5 minutes to generate MiniSoC
<ysionneau> oh, that's cool
<ysionneau> what was the issue?
<_florent_> it's the L2 cache that is not recognized as a memory...
<_florent_> in gensoc, you only have to import simplify:
<_florent_> from migen.fhdl.simplify import *
<_florent_> and apply FullMemoryWE to wishone2lasmi:
<_florent_> self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master()))
<_florent_> that's all
<ysionneau> ok nice
<_florent_> it should be fixed in the next releases of Vivado
<ysionneau> jboulder: please apply the following patch : http://pastebin.com/qU4N9mi2
<ysionneau> (or do the manipulation florent gave and go back to using Vivado)
<ysionneau> (just one line to change, to be clear, the line beginning with "set_property")
<ysionneau> I can't test myself though, I only have ISE webpack which does not support kintex 7 xc7k325t device :/
<jboulder> ysionneau, we're going to use user_clk, not user_gpio, which doesn't need this constraint anyway
<jboulder> (This is the SB boss-man)
<jboulder> (who now has the keyboard)
<ysionneau> ah, the programmable 200 MHz oscillator
<ysionneau> then you can just remove this constraint
<ysionneau> remove the line completely instead of applying my patch
<jboulder> no, the SMAs which are meant to be used as clocks, as opposed to gpio
<ysionneau> right, user_sma_clock_p
<ysionneau> which is ball number L25
<jboulder> k29/k28
<jboulder> and we're going differential
<ysionneau> humm k29/k28 is the "user_clock" (programmable oscillator)
<ysionneau> the user_sma_clock_p/n is l25/k25
<jboulder> ah right
<jboulder> thx
<ysionneau> what can I do to help so far?
<jboulder> have you built the 64-bit conda packages?
<ysionneau> nop, but I can try right away
<ysionneau> the only package which poses issues on 64 bits machine is "artiq" right, because of the GUI?
<jboulder> there should be no 64-bit issues whatsoever on linux
<jboulder> (for the GUI)
<jboulder> the GUI is totally independent from 32/64 afaict
<ysionneau> I mean, last time you said you tried the conda packages, you said everything worked fine except the GUI
<ysionneau> IIRC you tried the 32 bits packages on a linux-64 machine
<GitHub7> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/xfMy
<GitHub7> misoc/master 09fbbca Florent Kermarrec: gensoc: cpus now directly add their verilog sources
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* ysionneau afk eating
<jwbritto> (Joe again...) We have successfully programmed the KC705. RTIO output to the TTL lines works.
<jwbritto> SB is figuring out some timing-related issues for programming the DDSs.
* ysionneau is back
<ysionneau> awesome!!
<jboulder> kc705 flash access is buggy
<ysionneau> issues while executing BIOS? or loading the runtime?
<jboulder> writing flash, running the bios from the flash after bitstream loaded from jtag\
<ysionneau> hum :/
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<ysionneau> weird, seems like a normal quad spi nor flash that we should support
<jboulder> there is no such thing as "normal" hardware
<jboulder> or at least, normality doesn't mean trouble-free ;)
<ysionneau> unfortunately :p
<ysionneau> meanwhile, I have issues building llvm under Fedora 64 bits ...
<ysionneau> hitting some gcc 4.9 issues
<ysionneau> http://gcc.gnu.org/gcc-4.9/porting_to.html < Header <cstddef> changes
<ysionneau> -_-
<jboulder> worked fine with arch and linuxmint 64-bit here ...
<ysionneau> ok
<jboulder> I didn't have to edit any source file
<jboulder> maybe your gnu/autocrap script is doing the wrong thing?
<ysionneau> maybe you had gcc 4.8?
<jboulder> I'm pretty sure arch was 4.9
<jboulder> linuxmint 4.8
<ysionneau> anyway, on Debian Jessie it works fine, even with gcc 4.9 :/
<jboulder> is there any particular reason you'd need fedora?
<ysionneau> no, I should just switch to Debian
<ysionneau> doing it right now
<ysionneau> well, I guess I will finish that tomorrow, calling it a day!
<ysionneau> good luck with spi flash debugging
<jboulder> ysionneau, why did you remove some of the TIG constraints?
<jboulder> as well as the definition of GRPrtio_clk
<ysionneau> I saw that the ppro was generating a rtio clock at 125 MHz from the 80 MHz sys clk
<ysionneau> but since kc705 system clock is already at 125 MHz I just connected the sysclk to the rtio clk
<ysionneau> maybe I removed too many constraints
<jboulder> the constraints that are left right now don't do anything afaict
<ysionneau> yes I guess my constraint changes are wrong :/ sorry about that
<ysionneau> going to bed now, see you!
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