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GitHub153 >
artiq/master 614a96a Sebastien Bourdeauducq: tools/file_import: use python 3.4 importlib API
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GitHub153 >
artiq/master 656099a Sebastien Bourdeauducq: artiq_run: sort result output alphabetically
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GitHub153 >
artiq/master 170a626 Sebastien Bourdeauducq: tools/file_import: support import of modules importing from their directory
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GitHub88 >
migen/master cea1551 Yann Sionneau: mibuild: support pin names in IO extensions
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GitHub88 >
migen/master 5bb1c78 Yann Sionneau: mibuild/kc705: add FMC connectors
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GitHub110 >
artiq/master e6d0fc2 Sebastien Bourdeauducq: benchmarks: add copies of ddb/pdb
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GitHub110 >
artiq/master 3543dc3 Sebastien Bourdeauducq: Revert "tools/file_import: use python 3.4 importlib API"...
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GitHub110 >
artiq/master d484b3a Sebastien Bourdeauducq: tools: add missing import
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travis-ci >
m-labs/artiq#21 (master - dda5c16 : Sebastien Bourdeauducq): The build passed.
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GitHub60 >
misoc/master 4c9554b Florent Kermarrec: gensoc: call do_exit after SoC is built
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GitHub60 >
misoc/master 5500c41 Florent Kermarrec: move lm32/mor1kx submodules to extcores
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misoc/master 9ebb8f8 Florent Kermarrec: remove verilog and move mxcrg.v to misoclib/mxcrg
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_florent_ >
sb0: thanks for the commits
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_florent_ >
can you just do an update of LiteX in MiSoC, a CSR was missing on the MAC which cause the microudp.c to generate in all case software preamble/crc
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_florent_ >
with that, ethernet is working on Mixxeo/KC705
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_florent_ >
I'm integrating lwIP, RX is OK for now...
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GitHub89 >
artiq/master 3c50610 Yann Sionneau: pyon: bytes support
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GitHub89 >
artiq/master 05824fd Sebastien Bourdeauducq: lda: style
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GitHub89 >
artiq/master dc132bd Yann Sionneau: lda: fixes
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GitHub168 >
misoc/master 6db831e Florent Kermarrec: update LiteX
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m-labs/artiq#22 (master - de4a15c : Sebastien Bourdeauducq): The build passed.
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