rellla changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi - *only registered users can talk*
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<mirko> is audio via spdif/coax supported on h6? briefly scrolling through the dts(i) files i see definitions in arch/arm/boot/dts/sunxi-h3-h5.dtsi - but but that's it
<mirko> ah, in the megous branch there's also spdif defined for h6
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<jernej> MoeIcenowy: Do you know what happen to V3s analog codec? it seems that there is V3s specific code in the driver but nothing in DT
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<mirko> hm, anybody an idea where PH7 is located on the orangepi3? doesn't appear to be part of the exposed pin header. it's supposed to be s/pdif. or can i even map s/pdif to any arbitrary gpio?
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<jernej> mirko: According to OPi3 schematic, SPDIF is not exposed at all
<jernej> and no, you can't remap it to arbitrary pin
<jernej> in fact, spdif can be only routed through PH7 on H6
<mirko> jernej: pity, thanks
<mirko> jernej: did you check the pin header(s) or it's not accessiable from anywhere on the pcb?
<jernej> download OPi3 schematic and search for PH7
<jernej> you'll see that it's not connected anywhere
<mirko> i see - and it looks like being the only single pin not being connected to anywhere..
<mirko> ah, well, PL6, too - shame
<mirko> not doubting, just out of curiousity: how do you know PH7 is the only pin spdif can be routed through? is that part of the h6 datasheet?
<mirko> ok, i can see the user manual mentioning swa_out only together with ph7
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<jernej> it can be confusing, spdif is referenced as One Wire Audio in datasheet
<jernej> s/referenced/referred/
<jernej> another good source of such information is pinctrl driver
<mirko> figured that out by now - hence mentioning swa_out
<mirko> ok, will take a look, thanks
<mirko> but re SWA - what actually confusing me: it's described as One Wire Audio (as you said) - however it actually has 3 lines (OUT, IN, CLK) - how is that one-wire?
<mirko> i mean, i know spdif is, but swa only mentions being spdif compatible (via swa_out) - still having 3 wires..
<jernej> I don't know enough about this peripheral to answer that
<jernej> maybe it's similar to I2S controller which actually supports I2S, PCM and TDM modes
<jernej> e.g. similar enough to be supported with one peripheral
<mirko> i see..
<mirko> interesting, the term OWA seems to be used (created?) by allwinner only
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<mru> probably to avoid mentioning some trademark
<mru> they don't say i2c either
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<mirko> mru: was thinking the same (trademark), however i never heard of s/pdif having a(n optional) clock line - so i figured that's owa specific
<mru> s/pdif is just the one signal
<mru> that's the point
<mirko> ok, but then i'm even more curious about what's the clk line in OWA is supposed to do
<mru> what clk line?
<mirko> mru: OWA - according to Allwinner datasheets - consists of 3 wires: OWA_OUT, OWA_IN and OWA_CLK
<mirko> OWA_OUT is s/pdif (compatible) obviously
<mru> oh, that's probably just an input for an external clock reference
<mru> not part of the interface
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<mirko> hm - not sure how that would/could work when owa_out already has everything on its line (incl. clk/sync), but it's described as "One Wire Audio Master Clock".. *shrug*
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<mru> oh wait, it's just an ancillary output
<mru> if I'm reading between the lines correctly
<mirko> datasheet says it's an output indeed
<mru> there's an "mclk output enable" control bit
<mru> it's probably intended for synchronising other circuitry
<mru> you might use it to clock an adc, for instance
<mru> whatever you connect the spdif signal to obviously doesn't need it
<mirko> was wondering about that :) - anyway, i was just curious.
<mirko> there's even a "MCLK Clock Divide Ratio"
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<Ixnus> jernej: do you have v3s board - which one?
<jernej> Ixnus: I don't have any v3s, I'm just looking into R40 analog codec and I noticed that V3s analog codec is most similar
<Ixnus> Do you have BPI-M2 Berry or BPI-M2 Ultra ?
<Ixnus> https://forum.armbian.com/profile/14216-juanesf/ https://github.com/juanesf/ has said somewhere that he got audio working on v40/r40 and linked to his patches but can't find it now
<jernej> Ultra
<jernej> meh, it's not hard, I just wanted to know the reason
<Ixnus> good luck, and thank you and LE !
<Ixnus> Wonders what happened with that 3 x SATA speed patch got merged but never posted test results.
<Ixnus> Mainline with/without the patch vs BSP on A10/A20//R40/V40
<mru> nvme is where the speed is :)
<mru> though not so much on sunxi, I guess
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<wens> karlp: did you assign the MCLK (macro is CCU_CSI0_MCLK or something) output as the ov5640's xclk ? also muxed the MCLK pin?
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<Ashleee> btw the Tanix that I accidentaly shorted is fixed. Only after repairing the trace I found out it was straight from the power barrel jack so I could have used much larger pads to solder to :)
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<karlp> wens: not sure? this is my current diff vs the stock dts: https://paste.centos.org/view/d537d16a
<karlp> I've added a pio entry for csi_mclik_pin, and tried to add the ccu entry, but not sure.
<karlp> I've got the xclk on line 129..131, tried to mux it on line 76, and tried to register it on line 68, that's the piece I'm least sure on though
<wens> karlp: maybe try setting vcc-pe-supply in the pio node? might be the pins aren't properly powered
<karlp> which pins?
<wens> the pe pingroup
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<wens> hmm... nothing on the schematics to help
<karlp> no, and all four test points have either 1.5V or 2.8V which looks ok.
<karlp> the pin groups are defined where?
<wens> on the socs, sometimes there are separate power rails for each pin group (A - I)
<wens> that doesn't seem to be the case for PE* on H3
<karlp> this person says they have it working on the same hardware, and I cna't see any obvious difference, but they've only shared a decompiled dts from the whole tree: https://forum.armbian.com/topic/13238-ov5640-device-tree-overlay-for-orangepi-one-h3/?do=findComment&comment=104350
<wens> if you set everything on by hand (pinmux, clk, gpios), can you at least see it using i2c-detect?
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<karlp> no. but I'ðve heard conflicting reports on whether i2cddetect sees it anyway
<karlp> I don't know how to seup the clock by hand anyway, but I'd be more than happy to try
<karlp> I get some results from i23cdetect, but nothign at 0x3c where it should be, and manually trying i2cset 2 0x3c 0x03 0x0a, and i2cget 2 doesn't give me anything either, which is theoretically attempting to read the id register
<karlp> I could manually set the gpios to get the regualtors working, that's ok.
<karlp> I can maybe try manually doing the enable/standby pins too, but I'm concerned abotu the clock, a few reports say you won't get any response until it's clocked.
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<wens> karlp: poke the pio and ccu registers by hand using devmem to mux and enable the mclk
<wens> correct, it won't respond until it's clocked
<karlp> got a link to the register map for that?
<karlp> ok, think I found them in the h3 data sheet rev 1.2 from sunxi
<karlp> csi is at right, devmem says csi_clock register is all zero
<karlp> devmem2 readback after writing fails though, which is not convincing
<karlp> nope, reading the wrong offsets.
<karlp> ahha, ccu wasn't enabled for csi mclkc out
<karlp> hrm, modprobe clears it agian though
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<karlp> so that's the ccu-> csi clokc register at 0x1c20134, just bit 15 shoudl eb enough, ov56450 can take 6--27Mhz,
<karlp> PE Configure Register 0 already has 0x2 for "CSI" correctly though, so I guess that bits ok.
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<karlp> so, yes, CCU CSI mclkc gate is not correct, but i2cdetect still fails after that, (gives rotating mixed replies) and modprobe ov5640 after manually setting it clears CCU again, and still fails to read the i2c chjip id
<karlp> csi-mclk-pin on PE1 appears to be correctly muxed to CSI though
<karlp> I unfortunately have to go soon though but will read any scrollback. any more tips very much appreciated
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<wens> the ov5640 driver seems to disable the clock if it the camera is not active, or if the probe failed
<wens> rotating mixed replies sounds fishy though. are you probing the correct bus?
<wens> also, since you are not getting anywhere, might be worth checking the connector and cable?
<karlp> yeah, it's not comforting: https://paste.jvnv.net/view/scsWa
<karlp> csi-2ic is twi2 from the schematics so, I believe so.
<karlp> only other i2c device on the board is the pwoer rg on the s-twi interface for the core
<wens> It might be the cable you are using actually reverses the pin order
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