rellla changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi - *only registered users can talk*
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<plaes> jo0nas, jonasbits: not sure which one of you is improving the wiki for Olimex devices, but there's also this quirk needed for Lime2 (and possibly other) devices: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9567832aba7f48834d28e3174909149c904808c8
<jo0nas> that's me
* jo0nas taking a look...
<jo0nas> yes - I noticed that already during my recent overhaul of the wiki page - thanks!
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<jo0nas> plaes: I now proposed a patch to enable micrel support: https://patchwork.ozlabs.org/project/uboot/patch/20200809094851.4037443-1-dr@jones.dk/
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<hexdump0815> jernej: Ashleee: i gave the rank=1 hack a try on my h6 box and it does not work - but i'm getting a different error mesage with it - maybe some other change is required too? - here are the different outputs
<hexdump0815> jernej: Ashleee: https://pastebin.com/raw/yNV600zW
<jernej> hexdump0815: It would be really useful if you could do DRAM register dumps like Ashleee did
<jernej> so we can compare registers
<hexdump0815> jernej: Ashleee: can you maybe paste me some steps to do? problem is that i only have read-only serial as i was not able to find the tx pad on the board ...
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<hexdump0815> jernej: here is the md on the libdram hybrid u-boot run via boot.scr if that helps: https://pastebin.com/raw/3V5SiinU
<hexdump0815> jernej: can you please send me a diff with the proper printk for dumping the registers out in mainline u-boot? then i could buuld and run that too ...
<hexdump0815> jernej: i just looked at the old irc logs - which region to actually md dump? 4002000 or 0x4005000 or something else?
<jernej> I don't have code for reg dump, hopefully Ashleee still have it
<jernej> DRAM is from 0x04002000 to 0x04006000
<jernej> this region contains 3 things - controller, phy and probably some glue logic
<jernej> so whole range is important
<jo0nas> plaes or others: I would appreciate someone skilled writing C code to port this Micrel KSZ9031 PHY bugfix from Linux: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3aed3e2a143c96
<jo0nas> I can help test as needed, but won't try write the code
<hexdump0815> jernej: ok then my dump should have it all in already - but just in case here is the 0x04005000 dump as well: https://pastebin.com/raw/WkAStfXn
<hexdump0815> Ashleee: whenever you are around again, can you please pastebin me a diff of your register dumping printk for mainline u-boot?
<Ashleee> sure hexdump0815
<Ashleee> sec
<Ashleee> hexdump0815, https://pastebin.com/raw/55sWd5yX -- you can ignore the "writel(0x00010237)" line if you changed ranks=1
<jernej> better just remove it, ranks=1 makes things worse
<hexdump0815> Ashleee: thx a lot - let me try that :)
<Ashleee> np
<hexdump0815> Ashleee: jernej: hm - i added the printing but i still do only get "DRAM:This DRAM setup is currently not supported." - maybe it does not even come to the deug prints in my case?
<Ashleee> yeah
<Ashleee> copypaste the for (xdebug..) few lines above
<Ashleee> which device do you have hexdump0815 ? TX6 as well or the Eachlink?
<hexdump0815> no its some noname box with just printed h6 and 6k on it :)
<hexdump0815> the error i get is in "Check for dual rank and half DQ ..." - any idea?
<jernej> hexdump0815: this is caused by ranks = 1
<jernej> you should leave it on 2
<jernej> and also remove the line Ashleee mentioned, it does same thing
<hexdump0815> same error still with rank on 2 and the 0x00010237 write removed from the patch
<hexdump0815> i have just removed that panic and this is what i get then: https://pastebin.com/raw/dLbYDUe0 - does that make any sense?
<Ashleee> yeah that's the memdump
<Ashleee> now go byte for byte and compare it to the libdram one :)
<Ashleee> and check against the zynq mp specs and the struct in source :D
<hexdump0815> ooops - i think this is a bit beyond my skill level :)
<Ashleee> heh
<Ashleee> I'm making a lunch and then driving away, I can check later today
<Ashleee> (maybe 6 - 7 hours from now)
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<hexdump0815> Ashleee: that would be cool - i'll keep watching the irc then tonight
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<Ashleee> ok checking out the DTCR regs it seems that DTRDBITR is off by one bit (0x40)
<Ashleee> and then the DTCR1's RANKEN 0x03 vs 0x01 and RDLVLEN
<Ashleee> no idea which can be the problem if it doesn't work with ranks = 1 either
<Ashleee> and then there's some numbers in delay lines which are 0 on libdram
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<Ashleee> interesting that it throws only CAWRN and not CAERR
<hexdump0815> Ashleee: based on the differences you mentioned would it make sense to change something in u-boot to try to make it work?
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<jernej> and test?
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<jernej> hexdump0815: which config you're using on U-Boot mainline?
<jernej> it seems as if LPDDR3 would be selected instead of DDR3
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<hexdump0815> jernej: btw. are there any plans to submit a ddr3 tv box config to mainline u-boot? i think the mainline kernel has the tx6 dtb in it, so maybe its dtb and config could be added to u-boot too?
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<hexdump0815> jernej: i can try to set them to 0 - shall i do it with rank=1 or rank=2 and with that panic put back or leave it commented out?
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