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<
MoeIcenowy>
jernej: BTW I have a H6 board that uses AC200 FE phy
<
MoeIcenowy>
If you have no test device I can test on it ;-)
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<
wens>
the gpu clocks will get disabled if they aren't being used
<
wens>
the gpu
*might* have a controllable power switch in the PRCM, but that hardware block is mostly undocumented
<
KotCzarny>
wens, is turning off clocks enough for power save?
<
KotCzarny>
one could assume if nothing ticks, no significiant power should be drawn, as it's not power/voltage regulator
<
KotCzarny>
i wonder if allwinner could be coerced to document prcm for h3/h5/a64/a20
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<
suprothunderbolt>
anyone got wayland working on a64?
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<
suprothunderbolt>
or accelerated QT :)
<
superprower>
suprothunderbolt: Martijnb Braam from postmarketOS got it working on PinePhone devkit (uses A64, IIRC).
<
suprothunderbolt>
I've got the kernel module loading fine but wayland doesn't find anything and neither does anything else...
<
suprothunderbolt>
egl wise
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<
suprothunderbolt>
still haven't got a working accellerated qt on this, not sure what is wrong...
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<
jernej>
MoeIcenowy: Thanks, but I have Tanix TX6 STB to test AC200 EPHY patches
<
jernej>
Fun, 24M clock for AC200 is provided by PWM
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<
MoeIcenowy>
jernej: WHAT?
<
MoeIcenowy>
the PWM should be configured to output a clock?
<
MoeIcenowy>
so it's PB19 that is the clock input of AC200?
<
KotCzarny>
they've save3d 24M osci
<
jernej>
yes, but now I think it uses bypass functionality, which just bypasses whole PWM block and connects OSC24M directly to PB19
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<
MoeIcenowy>
how to bypass?
<
jernej>
so, it's ok, just weird it has to go through (bypassed) PWM block
<
jernej>
it has bypass bit
<
mru>
very tiny jumper
<
jernej>
datasheet has info only for one channel, but clearly HW has two PWM channels
<
jernej>
and second one is internally connected to (internal) PB19 pin
<
jernej>
mainline PWM has some bypass logic in it, however, bypass bit is never set
<
jernej>
I have to study code a bit
<
anarsoul>
jernej: IIRC it just bypasses divider
<
jernej>
so, nothing to worry?
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<
jernej>
anyway, to generate 50% duty cycle it would need at least 48MHz clock, right?
<
jernej>
I never used PWM before
<
jernej>
in Linux :)
<
jernej>
"If the bit is set to 1, PWM0’s output is OSC24MHz."
<
jernej>
I'm not really sure if this is only about divider
<
wens>
IIUC it bypasses the whole PWM mechanism and just outputs the input clock
<
wens>
which is OSC24M
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<
wens>
should be doable, but then again there's also clk-pwm
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<
jernej>
what's clk-pwm?
<
wens>
a driver that takes a pwm and provides a clk? :)
<
wens>
drivers/clk/clk-pwm
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<
jernej>
should I use that instead of PWM directly?
<
wens>
I think so, to model them properly
<
jernej>
anyway, that bypass functionality has to be added to pwm driver anyway
<
wens>
if you use clk-pwm, I doubt it would use the bypass
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<
jernej>
I have to set it to 24 MHz, which is only possible with bypass. Or did I miss something?
<
wens>
there is a /1 divider, no?
<
wens>
oh, nevermind
<
jernej>
yes, but what would be the period? 1? 0?
<
wens>
yeah, looks like you need to add support for bypass as "24 MHz 50% duty cycle"?
<
jernej>
albeit period 0 may also work
<
jernej>
per datasheet, period 0 means 1 cycle
<
jernej>
however, signal might be more noisy
<
jernej>
yes, "24 MHz 50% duty cycle"
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<
wens>
wonder if the pulse mode and polarity configurations still work under bypass
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<
libv>
jernej: is there a device page for the tanix tx6 stb?
<
jernej>
no, not yet
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<
markvandenborre>
:-)
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<
jernej>
do you mind take a look?
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<
MoeIcenowy>
jernej: I think you can just use reg_bits = 16
<
jernej>
MoeIcenowy: but you must write high byte into register 0xFE
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<
MoeIcenowy>
I never remembered this...
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