#linux-sunxi on 2018-07-15 — irc logs at freenode.irclog.whitequark.org

2015-02-18 19:37 Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi

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10:47 <montjoie> I have problem understanding sun6i-rtc bindings, it create osc32k clock, but osc32k already exists in DT

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10:53 <MoeIcenowy> montjoie: the SoC has a internal mux which is the input of CCU

10:54 <MoeIcenowy> it muxes between external 32k crystal and internal 16M rc divided 32k

11:05 <montjoie> but if I respect the binding it crash*

11:05 <montjoie> I have a patch for not crashing and just fail

11:05 <montjoie> but it fail when respecyin the binding

11:06 <montjoie> and nobody respect it

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16:23 <willmore> MoeIcenowy, Is the external RTC XTAL "32.000K" or it is the more standard 32.768KHz? I assume the "16M' is really 16.000MHz.

16:23 <wens> willmore: internal 16M RC oscillator is at or around 16 MHz, given it's RC, not very accurate

16:23 <willmore> 16.000MHz to 32.000MHz is trivial as it's /500 (assuming you aren't stuck to power of two divisers)

16:24 <willmore> wens, ahh, okay.

16:24 <willmore> Missed the 'internal'.

16:24 <willmore> Then the error individing ~16M down to ~32KHz is not an issue.

16:24 <willmore> Sorry.

16:39 <MoeIcenowy> willmore: xtal 32768

16:40 <MoeIcenowy> wens: strangely on H3 it's only ~13MHz

16:42 <MoeIcenowy> by comparing it with iosc (compare ar100 with iosc mux and osc24M-based timer)

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19:18 <montjoie> MoeIcenowy: so i dont understand, how can two clock exists with the same name ?

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21:23 <ElBarto> MoeIcenowy: 14" for my pinebook

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23:14 <smaeul> willmore: MoeIcenowy: On my A64s/H5s IOSC is usually around 14 MHz (again tested by running AR100 from IOSC and comparing with OSC24M)

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23:41 <willmore> Is there, maybe a register that holds a tuning value for the internal oscillator? A lot of microcontrollers with internal oscillators have a register that the chip reads at startup which tunes the osc to where it's supposed to be--this helps offset process variations.

23:41 <willmore> Could there be such a thing for the Allwinner chips?

23:42 <willmore> I would assume it's not automatic, but instead needs to be read out of one of the OTP fields somewhere.