<icenowy[m]>
speed up is not the critical thing now
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<wens>
jernej: a proper board design? :)
<wens>
jernej: AFAIK Allwinner hasn't added voltage switching support for mmc0 in any of its chips, except probably the A80
<wens>
jernej: so the fastest it can go is 25 MB/s
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<icenowy[m]>
I think at least it's possible
<icenowy[m]>
but in no reference design
<wens>
problem is there is no dedicated VCC for PF pins
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<f11f12_>
jernej: for HDMI I'd like to know if a hot plug edge should trigger a HDMI irq (GIC 90). In the 3.10 kernel there is a thread polling the hpd bit.
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<f11f12_>
on the LVDS side: I've hooked up a panel, using the tcon0 test image generator I have output (timing is ok). I have a tcon_top, tcon0/1, mixer0/1, display_clocks and a de with two pipelines.
<f11f12_>
The diagram in the manual shows DE0->mux-A->tcon_lcd0->mux-B->LVDS0. I assumed the 'DE0' is 'mixer0', and the mixer0 will run the DMA transfers. I could not find any documentation in the mux-A, my mux-B is probably correct as I can get tcon0 test output to LVDS.
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<f11f12_>
/dev/fb0 is present, setting modes/timings is ok.
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<hanetzer>
ugh. don'tcha hate it when you had something that kinda worked, and then you rebase against upstream and it doesn't work at all anymore?
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<jernej>
icenowy[m]: wens: Ok, but that is probably not the reason why I get only about 2.5 - 3 MB/s read speed on H6, while on H3 is much higher.
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<jernej>
f11f12_: HDMI HPD should trigger HDMI interrupt, which in R40 case should be 120 - 32 = 88
<jernej>
ah, sorry, looking at wrong manual
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<jernej>
it's 90 - 32 = 58
<f11f12_>
:-) Just checking the same
<f11f12_>
ok, got that one too.
<jernej>
I think "MUX" in manual is actually TCON-TOP
<jernej>
can you paste your TCON-TOP DT node somewhere so I can check what you have there?
<wens>
jernej: you mean restricting it to not switching parents?
<jernej>
f11f12_: additionally, you have to add CLK_SET_RATE_PARENT flag to hdmi_clk in clk driver if you want to have any hope seeing something on the screen
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<f11f12_>
the tcon1 test for hdmi outputs nothing yet. For LVDS I had to set a bit in a undocumented register (0x1c71084).
<f11f12_>
I patched ccu-sun8i-r40.c with the minimum rate.
<f11f12_>
init.flags = CLK_SET_RATE_PARENT; is set in sun8i_hdmi_phy_clk.c
<jernej>
wens: I mean some mechanism which would take care that clocks don't interfere between each other
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<jernej>
wens: one could be assigning parents in DT and then somehow mark them not to change parent
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<jernej>
wens: the other would be checking if parent clock is already taken or fixed and select another one
<jernej>
I mean parent PLL
<wens>
I thought clock rate protection in sun4i-drm was merged?
<jernej>
wens: so that may actually already work as expected...
<jernej>
wens: if only TCON is first clock which sets desired frequency
<jernej>
wens: but I think that this is not enough, since in clk driver you can't check if clock is taken (or "locked") and rate changing on such clock "succeeds" with doing nothing
<jernej>
at least I remember it in this way
<f11f12_>
jernej: for the V40 I also need to set the HDMI input src and clk gates (sun8i_tcon_top_set_hdmi_src and sun8i_tcon_top_de_config). I'll test it manually
<f11f12_>
does tcon_top only have registers at 0x00, 0x1c and 0x20? thats all the manual lists vor V40
<jernej>
tcon top details are in TCON section in R40 manual
<jernej>
but as far as you are concerned, those registers should be enough
<_bielski_>
beeble: I will try mainline. Just in the past when I was putting the SD card image together I have taken the u-boot linked by the github user 'longsleep', I assummed that there is a reason why it works like that. That's the only reason.
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<f11f12_>
hey! tcon_top registers set and I've got HDMI test output :-)
<jernej>
ah, I remembered why don't you see anything on the screen
<jernej>
actually, R40 has mixers on same base address as others SoCs: mixer0 - 0x01100000, mixer1 - 0x01200000
<jernej>
you shouldn't change size in the driver
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<f11f12_>
jernej: what is 'MP' in the memory map?
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<f11f12_>
I'll fix my dt
<wens>
f11f12_: Mixer Processor, a mem-to-mem 2D compositing engine
<wens>
not the same as DE 2.0 mixer
<wens>
I guess that's your culprit
<f11f12_>
wens: thanks!
<f11f12_>
yes, indeed!
<wens>
f11f12_: did you actually read the relevant sections in the manual? or did you think that, hmm this looks close enough, and used it
<wens>
DE 2.0 is in the "Display" chapter, while MP is in the "Graphic" chapter
<wens>
huge difference
<f11f12_>
wens: for the V40 i have no documentation on the DE2.0, the DE2.0 manual does not list the V40
<jernej>
f11f12_: since all DE2.0 are much or less the same
<jernej>
*more
<wens>
f11f12_: well the V40 or R40 manual does actually have a one page description for DE 2.0, and a whole chapter for MP
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<f11f12_>
wens: the MP chapter only lists we to mem, but the DE chapter lists just specs. From the specs it looked similar to the A83t, so I went with that.
<wens>
so how did you manage to put in the wrong address for all the mixer blocks...
<jernej>
f11f12_: what compatibles are you using for mixers?