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<nycto>
hi there
<nycto>
how do I enable/disable the otg port on a orangepi zero for example? doesn't work anymory by modifying "/sys/bus/platform/devices/sunxi_usb_udc/otg_role"
<nycto>
Kernel is: 4.14.14-sunxi
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<pmpp>
nycto: mainline does not work that way, use device tree to enable/disable peripheral mode
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<wens>
dgp: looking at some designs, that's probably ok to do?
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<sensille>
and does anyone know what the spi dma can do on the H5?
<sensille>
-and
<sensille>
i'm trying to find a transfer mode to a device without much cpu intervention
<buZz>
sensille: if its just one way, how about HDMI ;)
<buZz>
hehe
<buZz>
sorry, silly suggestion ;)
<sensille>
ok, here comes my restriction: the device has to do the flow control
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<sensille>
spi and uart only have 64 byte buffers, which would require very regular serving by the cpu
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<beeble>
device controlled flow control and spi does not really mix?
<sensille>
probably not :-/
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<sensille>
4-wire uart has flow control, but only 64 byte buffer
<beeble>
usb is not an option?
<buZz>
hmhm, usb is quite fast, and low cpu load
<sensille>
the other side is an fpga. i could probably find an usb core for it
<buZz>
or glue a atmega32u4 on it ;)
<sensille>
but that is a lot of overhead
<beeble>
on an fpga you would need to add an phy
<buZz>
depends on how many million of products you're making :P
<beeble>
-n
<buZz>
for 1, i'd totally do the atmega :P
<buZz>
i mean 1 , not 1M
<sensille>
the fpga eval board has a phy, but that makes moving to different fpga more complicated
<beeble>
what is your application and what kind of efforts in the fabric are you willing to do?
<sensille>
someone suggested making the device the spi master
<beeble>
don't do spi
<sensille>
and the H5 the slave
<beeble>
especially not in that direction
<sensille>
beeble: application is a 3d printer. the fpga does the motion control and needs quite bulky data
<beeble>
ok thats to hard
<beeble>
the fpga could do spi device
<sensille>
and must never run out of data
<beeble>
but you don't want to do spi slave on a linux based stack
<buZz>
why not have a buffer?
<buZz>
like marlin does on RAMPS
<sensille>
fpgas don't have much RAM
<buZz>
correct
<buZz>
you can implement ram in vhdl though :P
<buZz>
hehe
<sensille>
distributed ram
<buZz>
or just add a ram chip?
<sensille>
but just because i can't properly transfer data?
<buZz>
well, you assume you cant
<sensille>
beeble: what would be too hard?
<buZz>
ramps/marlin uses a 2kb buffer typically
<buZz>
and only runs out of data at quite high speeds for a 3D printer
<sensille>
buZz: yes. maybe a combination of a few kb buffer in the fpga + uart might do
<buZz>
like 150mm/s extruder speeds
<beeble>
sensille: my statement was to harsh with don't do spi. that is not universally true
<buZz>
yep, ramps/marlin uses normal uart for the data (over usb though)
<sensille>
i want to transfer a _lot_ more data than marlin
<sensille>
beeble: one idea was H5 as spi slave and feed data via DMA
<beeble>
sensille: that will end in pain :)
<sensille>
buZz: something like that, but with more finegrained jerk control
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<buZz>
sensille: i hope your design already uses trinamic drivers, or what's their name ;)
<sensille>
beeble: probably it will already start with pain
<sensille>
buZz: of course
<buZz>
good :)
<beeble>
sensille: what about using a cpu with a static bus?
<sensille>
beeble: i tried to read the H5 manual, but it doesn't explain much wrt spi/dma
<sensille>
it's not a high quality data sheet
<sensille>
is there a better source?
<buZz>
if you want documentation, use TI ;)
<buZz>
their docs are endless
<buZz>
so, like a beaglebone
<sensille>
beeble: what do you mean by a static bus?
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<sensille>
8 data lines, /rd, /wr?
<beeble>
sensille: parallel bus like used for sram. that is the lowest effort bus
<beeble>
yes
<sensille>
but it can't dma into the H5's memory
<sensille>
or being served automatically in any way
<sensille>
from H5's side
<Pe3ucTop>
Hey, still about SPI , why not use standart SPI master and FPGA SPI slave with interrupt ?
<sensille>
i haven't seen those buses in ages :)
<sensille>
Pe3ucTop: yes, interrupt for the flow control. that would be a low effort solution, but also probably produce lots of interrupts
<Pe3ucTop>
And you can make FPGA SPI slave with SPI Dual mode support (and will have enough speed) ?
<sensille>
a few MHz will suffice, so speed is not really a problem
<sensille>
i'm only concerned about the data running out
<Pe3ucTop>
sensille: if you will work with bigger packets, than there will be less interrupts than UART..
<sensille>
Pe3ucTop: that would require some buffering in the slave, but yes. but how will a larger buffer be handled in the host?
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<beeble>
making the fpga the bus master does not really sound like the better way. because your cpu has to generate/provide the data anyway. use a fpga with embedded sram as buffer. make whatever interface you can easily do on the fpga and serve it from the cpu
<beeble>
you could even do i2s :)
<beeble>
that works well for streaming data
<sensille>
yes, with the given hardware that seems to be the best option
<sensille>
can i generate interrupts from the gpio pins?
<Pe3ucTop>
from my experience, we have recently switched from FPAG UART (12.5 Mbps) to FPGA SPI Slave and get many benefits..
<beeble>
Pe3ucTop: having a synchronous interface will always be beneficial...
<sensille>
spi is even easier to implement in the fpga than uart, but that doesn't really matter
<beeble>
sensille: yes, but you have to check the datasheet. not all gpio banks are interrupt capable
<sensille>
and (sorry, i have no experience to *pi yet), is it possible to block from usermode on an interrupt event without having to write a driver for that?
<beeble>
select(2)
<beeble>
if using the sysfs interface
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<sensille>
that's great
<beeble>
with the char device probably too but don't know how without checking docs myself
<Pe3ucTop>
sensille: I would suggest to disable interrupt in slave device too, it's not goot to hold interrupt even if it's disable on host side.
<sensille>
Pe3ucTop: sorry, i don't understand. the slave side (the fpga) doesn't have interrupts?
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<beeble>
sensille: on h5 it looks like P[A,F,L] pins are interrupt capable (user manual 4.12.1)
<Pe3ucTop>
sensille: slave side(fpga) need to generate interrupts to host, but only when it is allowed..
<sensille>
another possibility would be to generate status messages (like queue low) via a different interface (uart), then the host app can just block on that
<Pe3ucTop>
Hey, do any body know is it possible to control P2WI (AXP22x PMIC) over I2C ? Direct/single device connection CPU - PMIC ..
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<buZz>
Pe3ucTop: which part are you asking about? if axp22x has i2c controls?
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<beeble>
axp22x is push/pull only iirc
<buZz>
it does have a i2c port on chip
<beeble>
not even sure if you can really do anything else then rsb
<sensille>
which means i can use uart with flow control and set up decent buffers in the host
<beeble>
buZz: but thats axp20x we are talking about axp22x :)
<Pe3ucTop>
buZz: there is many errors in doc, in description it's Push-Pull Two Wire Interface , but in other places still TWSI , even in signaling ..
<buZz>
beeble: i doubt allwinner is in business of reinventing wheels :P
<beeble>
Pe3ucTop: can't remember the place. somwhere it is described on a communication level
<beeble>
i can still remember when i had to sniff the bus and i can't use my standard i2c parser because of the iirc crc field
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<sensille>
do the drivers already support dma in some way?
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<Pe3ucTop>
sensille: UART buffers at host is ~4k , higher buffers you need to implement in application. UART looks like suport DMA, SPI do not support DMA in mainline.
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<sensille>
that sounds like uart is the way to go
<sensille>
also it seems to be able to go quite high with the clock rate
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<Pe3ucTop>
yes, I personaly worked with UART 12.5 Mhz clock , mostly receive dirrection, higher speed teoreticaly is possible.
<sensille>
great
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<sensille>
what distro can you recommend for a headless operation?
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<montjoie>
gentoo!
* hanetzer
<3 gentoo
<sensille>
been there, done that
<hanetzer>
I'm getting a talos workstation :)
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<sensille>
gentoo was a pain when i tried updates after 2 years
<buZz>
hanetzer: sweet :)
<hanetzer>
heh. yeah, you gotta keep on top of it :)
<sensille>
i'm not the type for that ;)
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<buZz>
sensille: tbh, i dont think i can think of any distro that wouldnt be fine for headless
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<buZz>
(assuming you dont install non-headless nonsense, like xorg)
<sensille>
armbian?
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<hlauer>
icenowy[m]: banana m2ultra: Yesterday I got the cpufreq driver running and set the max freq to 1080 Mhz like suggested by you.
<hlauer>
Unfortunately the device still dies during deb packaging of the kernel or whil running firefox. Any further ideas ?
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<buZz>
checked the powersupply yet?
<jonkerj>
my h3 boards die all the time when doing cpu-heavy tasks, I use megi's orangepi tree (including dvfs/cpufreq/thermal), I suspect the operating points are slightly undervolted
<buZz>
i run a H3 on 3.4.113 , probably a allwinner kernel
<buZz>
but it crashes approximately never
<KotCzarny>
3.4.113 is armbian kernel
<buZz>
ah, yes
<KotCzarny>
which started as aw kernel but got a bit better
<buZz>
that makes sense
<megi>
jonkerj: which version? 4.17-rc?
<buZz>
the heaviest stuff i do on it just loads ~1.5 core though
<KotCzarny>
make -j8 on kernel compile does a nice test
<KotCzarny>
and there is always cpuburn-a7
<KotCzarny>
:>
<megi>
KotCzarny: that's what I run to test my kernels/boards :)
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<KotCzarny>
yeah, and that's why i compile natively too
<megi>
though I'd not be so courageous to do it without a heatsink
<KotCzarny>
doable with sane dvfs
<megi>
it's probably doable with faster reading of thermal sensor values even with insane settings
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<megi>
so that kernel reacts quickly enough to even the fast changes in temperature
<jonkerj>
megi: 4.16.0-rc2
<jonkerj>
(and all versions before)
<buZz>
haha yeah, H5 without heatsink, even on idle , is -not- cool to touch :)
<buZz>
gotta finish soldering up so i can install the heatsink :P
<megi>
jonkerj: some RCs are buggy.
<megi>
does it reboot or lockup?
<jonkerj>
ok, but I had the same issues with 4.15, 4.14, 4.13 etc
<jonkerj>
reboot
<megi>
ok, I don't know, the settings in my tree are a bit overclocked, so it might be that
<jonkerj>
it's not a big enough problem to fix it for me :-)
<jonkerj>
since they reboot, they come back and are functional in no time
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<jonkerj>
and it's not too often
<megi>
ok :)
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<hlauer>
buZz: Hanging on a +5V rail of a PC which drove a bananapi too without any problems. 4.17-rc7, oppv1 are from the 3x kernel tree.
<hlauer>
soc is r40.
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<hitech95>
hi guys is there someone here that have a bpi m2m or similar hardware? I'm having a strange behaviour of the serial port. I'm new on allwinner socs so maybe is my fault. I'm connecting with 115200 8n1 without a proper image. I thing that i should have something on the outoput like a bootrom error or version
<hitech95>
I also added an sd with a proper image
<hitech95>
but the serial output is garbage. I tiple checked the gnd connection and is ok. I also tried with the scope and data frame is garbage i can't identify any frame
<hitech95>
suggestions?
<pmpp>
hitech95: with no emmc and no image soc fill boot via fel
<hitech95>
pmpp, no the serial is always garbage. If i put a valid image the status led blinks like if post is done ok and i get a lot of stuff out the serial but is not clear.
<pmpp>
if you are sure your image is valid then obviously your board is broken or uart speed invalid
<hitech95>
if you have other suggestions to take care of i will do. Right now i have no idea of what can i do.
<pmpp>
all that i can say is when using proper uboot and FEL you'll get that on UART https://wyz.fr/7yD
<pmpp>
if not throw the board away
<pmpp>
and mayte buy something from maybe other maker
<hitech95>
yup i warked on openwrt/lede stuff and porting so i know how uboot should look like :) the only part that i dont understand is the SPL
<hitech95>
pmpp, i'm making a product based on the R16 i bought the M2 magic to have a development kit while i'm making my own board
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<pmpp>
well good luck and don't make a banana ;)
<hitech95>
I hope, this diy project started bad... and got worse xD
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<pmpp>
hitech95: that bpi is A33, what is the spl config name ?
<hitech95>
pmpp what do you mean by spl config name? (sorry i'm noob with allwinner)
<pmpp>
hmm so where is your uboot coming from ?
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<hitech95>
pmpp, from the image done by bpi.
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<hitech95>
right now i'm installing the linaro toolchain to build my own uboot
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<pmpp>
yeah sounds better
<pmpp>
i have a couple A33 spl in fel installer but i don't have uart on my A33 soc to test correct init
<hitech95>
pmpp, oh ok. thx for the help. I have a dummy question. what is this SPL? why allwinner don't have the "standard" uboot process? Looks like that it load a script to boot the kernel. I worked on mips and uboot and the boot process is a lot simpler.
<pmpp>
the spl allow you to boot without rom support
<pmpp>
afaik boot0/1 that may be in nand
<hitech95>
uhm. still not gettin it. The bootrom look for SPL than SPL load UBOOT and uboot load the kernel via the boot.scr script?
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<Pe3ucTop>
Could anybody direct me to reasonable P2WI / RSB documentation , working on HW implementation and many unclear things, thought it's i2c compatible, but looks like it's not..
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<hitech95>
pmpp, still getting the same error. the fel-installer don't have the right board
<pmpp>
nothing on uart with a boot attempt with any A33 ?
<hitech95>
yes, also the soc stay in fel mode. no idea why
<pmpp>
it will stay that way until you send boot script
<hitech95>
now i moved to my netbook with linux so i can try sunxi-tool for linux
<pmpp>
indeed better use the latest uboot and tools
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<hitech95>
pmpp, ok done. with latest sunxi-tools on linux
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<paulk-gagarine>
for the folks interested in free boot software, there's the open source firmware conference this september: https://osfc.io/
<paulk-gagarine>
(what I mean by free boot software is what they mean by open source firmware, which is not what I usually mean by open source firmware, though)
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<hitech95>
guys does someone have a guide to port armbian for a new platform?
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<vagrantc>
does armbian actually rebuild all packages, or does it largely re-use debian packages from debian.org ?
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<pmpp>
i think it's full use, and mostly add uboot+kernel
<beeble>
vagrantc: debian/ubuntu debootstrap
<beeble>
depending on the flavor you choose
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<vagrantc>
that's what i thought, but reading a few things made me wonder
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<hitech95>
What is the best distro/build platform for an embedded device with eeprom? If i got correctly i have to think an eepromas an sd card. buit i would like to make partitions like "uboot", firmware (kernel + data), other partitions. Would that be possible?
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<beeble>
hitech95: your system will not fit into an eeprom. if that is what you are trying
<beeble>
(if you have a cpu that is capable to boot from eeprom...)
<hitech95>
beeble, pmpp, I have a emmc but i used to work with spi eeprom. I would to optain the same result. to make sure someone can't screw up the bootloader.
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<beeble>
what cpu are we talking about?
<hitech95>
A33
<hitech95>
or R16
<hitech95>
pmpp, now I have a fel booting board with UART log on serial0. But i don't have a valid linux image :) Thanks for the help :)
<KotCzarny>
spi is eeprom? isnt it just nor/nand flash?
<hitech95>
beeble, the board is the bpi m2 magic
<beeble>
you will need a spi nor flash
<beeble>
not an eeprom
<pmpp>
hitech95: so bpi's uart is good but lack of software, that does not sound new :p
<hitech95>
beeble, why i cant use the emmc?
<pmpp>
glad i could help
<beeble>
hitech95: you where talking about putting the bootloader into the spi storage
<hitech95>
pmpp, yup. I tried to boot the image for the olimex A33 all workis "fine". process starts I get a full log but somewhere it stop. I don't have a shell on uart.
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<beeble>
hitech95: and the bootrom only supports spi nor flash, not eeprom
<hitech95>
beeble, i would just use an emmc for all. bootloader and "firmware" and data. More or less like an android device with multiple partitions.
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<beeble>
in that case it will work. bootloader at 8k offset, check that your first partition starts after the bootloader