<DocScrutinizer05>
if yes then you probably should use that pin for connecting D2
<wpwrak>
ADV in are the little green ones, S... (and D...)
<wpwrak>
adC even
<wpwrak>
(led on adc) if i was to do this, B0, B1, or D6 would be best. they all have high drive strength and ADC in. not that high drive strength really matters that much, but hey, since we have it :)
<DocScrutinizer05>
how about PTB1 pin21?
<DocScrutinizer05>
aah ok, you already solved that
<DocScrutinizer05>
and *seems* red LEDs are best for photodiode
<DocScrutinizer05>
(not verified)
<wpwrak>
by the way, this one is a potential DNP LED. D1 is guaranteed to say.
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<DocScrutinizer05>
couldn't find my way for D1
<DocScrutinizer05>
ooh, con4
<DocScrutinizer05>
still lost
<DocScrutinizer05>
ugh, secure MCU
<DocScrutinizer05>
B0 you said? looks good
<wpwrak>
the other LEDs are just for debugging, not designed to be visible from the outside
<DocScrutinizer05>
just wondering about clock/speed of secure MCU
<DocScrutinizer05>
o.O
<DocScrutinizer05>
will it be fast enough to do more than 4 ADC / s?
<DocScrutinizer05>
or what's the rationale for 32kHz clock?
<DocScrutinizer05>
maybe it has a PLL that can create a real clock even from 32kHz?
<DocScrutinizer05>
or it has an internal oscillator?
<DocScrutinizer05>
TLV61220 running as long as battery provides power?
<wpwrak>
it has many clock options. normal operating speed would be 48 MHz core, 24 MHz bus
<wpwrak>
32 kHz is for the RTC. only draws a few nA
<wpwrak>
yes, boost is "always on", even if we have USB power. not entirely happy with the arrangement, but it seems difficult to do better.
<DocScrutinizer05>
aah ok. I just been worried about cpu grunt
<wpwrak>
(do better) i.e., low-voltage switches contain their own little boosters and are actually quite power-hungry
<DocScrutinizer05>
well, as long as boost doesn't eat power...
<wpwrak>
it does, of course :) but switches aren't much better.
<DocScrutinizer05>
the FB is already very high impedance
<DocScrutinizer05>
so how much quescent does it eat?
<wpwrak>
typical quiescent current is 5 uA
<DocScrutinizer05>
meh
<DocScrutinizer05>
:-)
<DocScrutinizer05>
nice
<wpwrak>
poor battery. never a moment of rest :)
<DocScrutinizer05>
ohmy
<DocScrutinizer05>
self dicharge will be higher
<wpwrak>
but yes, i think this is the sort of boost converter they also use in mice
<DocScrutinizer05>
ok, for the tresor code you possibly might change that to sort of gesture recognition on capacitive sensor
<DocScrutinizer05>
tap left, tap right, tap left, slide up, slide down, doubletap right
<DocScrutinizer05>
this sort of thing
<wpwrak>
right now it's sort of a pin
<DocScrutinizer05>
yeah, where you need to look closely and navigate carefully to the digit you need next
<DocScrutinizer05>
it still doesn't tell how to enter text or digits/pin
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<DocScrutinizer05>
anyway, seems you have a UI concept consisting of the elements "touch left, touch middle, touch right" for activation at least. probably those 3 digits together with pace/speed of enering them could make a convenient "gesture" to enter some "pin"
* DocScrutinizer05
drums a funny rhythm on table with three fingers
<DocScrutinizer05>
your current system lacks the time component
<DocScrutinizer05>
the "pen" idea is basically exactly what I suggested
<DocScrutinizer05>
just that the pen in my concept only writes as long as touch
<DocScrutinizer05>
the resulting pattern could get matched against a stored pattern
<DocScrutinizer05>
scaling in both X and Y direction
<DocScrutinizer05>
in X (time axis) only a 20% of scaling and even less of nonlinearity (distortion) allowed, in Y (slider pos) axis I'd allow even a 50% of zoom and nonlinearity/noise
<DocScrutinizer05>
the patter would look like . _ . -- ` / . \/
<DocScrutinizer05>
/ and \ are full range slides
<DocScrutinizer05>
stuff like ^ and v and V may also appear
<wpwrak>
(time component) that thing would move continuously. so time = y position
<DocScrutinizer05>
err yes
<DocScrutinizer05>
that's what I said
<DocScrutinizer05>
nope, I swapped X and Y
<DocScrutinizer05>
in your tap thing there's no time component. In the pen thing aiui there is no tap component, only slides
<DocScrutinizer05>
the "new quick idea" pen thing
<DocScrutinizer05>
I suggest to combine the two
<wpwrak>
yes, you could add "no touch" as additional information. but it may have other uses. e.g., to signal the end of the pattern.
<DocScrutinizer05>
end of pattern is "no touch event for >1s"
<DocScrutinizer05>
or N
<DocScrutinizer05>
fractions of a second
<wpwrak>
yes, there are many possibilities for the details. it's a matter of implementing it, trying to see how it works, refining it, etc.
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<DocScrutinizer05>
:-) my approach is different. implementation is negligible since feasible. It's the usability aka UI design that counts
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<DocScrutinizer05>
with a slide-only_one-touch-event input you need way longer to gather sufficient number if significant bits
<DocScrutinizer05>
or let me put it this way: the UI bandwidth is inconveniently low
<wpwrak>
i tend to discover lots of things about the usability of my designs when actually using them :)
<DocScrutinizer05>
yeah, and probably you won't implement an alternative concept unless the current one is comletely useless :-)
<DocScrutinizer05>
well, when you add pen-down / pen-up to your concept, and add a timer to detect end-of-input pen-up (which you'll need anyway to avoid trihhering on glitches) then you're already with my concept while still yours is a perfectly working subset
<DocScrutinizer05>
triggering*
<wpwrak>
the tricky bit is the pattern matching. capturing some doodle is easy, matching it is hard.
<wpwrak>
and the better the algorithm, the more "secret bits" it can extract
<DocScrutinizer05>
sure. but that doesn't differ between your and my concept either
<DocScrutinizer05>
no, since you can't enter with such precision
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<wpwrak>
yes, you have to compensate for the "noise". basically like a human recognizes signatures.
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<DocScrutinizer05>
I think simple X and Y shifting and zooming to adjust for best match will go a long way
<DocScrutinizer05>
then define match as "to points are less than distance Delta from each other"
<DocScrutinizer05>
two*
<DocScrutinizer05>
or think of drawing the reference pattern with a thick brush
<DocScrutinizer05>
the ratio of points of test pattern overlaying the "thick" reference pattern to those that don't is your matching factor which needs to be high enough
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<DocScrutinizer05>
zoom up and down a bit in X and Y and see if matching factor gets better (search maximum)
<DocScrutinizer05>
or you do some nifty math like FFT and compare wavelets
<DocScrutinizer05>
actually zooming on time axis is pretty simple
<DocScrutinizer05>
just adjust-zoom length of test pattern to reference pattern - as long as that doesn't mean more than 50% scaling
<DocScrutinizer05>
if you'd beed more than 50% it's a fail
<DocScrutinizer05>
need*
<DocScrutinizer05>
maybe even just 20 or 30%
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<DocScrutinizer05>
oh, it needs a special sort of "points" that match when in both reference and test pattern the same special sort of point at this time is present: no-touch
<DocScrutinizer05>
no-touch points have no (or a fixed 'out-of-band') position
<wpwrak>
well, i hope someone will pick up the idea and contribute something
<DocScrutinizer05>
probably a proof of concept could get done with those image magick tools and a script
<DocScrutinizer05>
the 'canvas' wouldn't need to be larger than 4x40 bit for a 2s pattern
<wpwrak>
why not in the simulator ?
<DocScrutinizer05>
because it's way simpler to have the whole thin on a high level of abstraction first
<DocScrutinizer05>
thing
<wpwrak>
you get input and canvas in the simulator ...
<DocScrutinizer05>
only when it works and you seen what happens on a 40x4000 canvas, using imagemagick tools, you slim the concept down to fit into this tiny MCU
<wpwrak>
probably more work this way. the sim runs on linux, so it has access to anything you want to add
<DocScrutinizer05>
just like you possibly design a PID controller in spreadsheet first, before you implement a tailored-to-purpose assembler program with the algo and parameters you found
<wpwrak>
well, just telling you that the simulator can do more than one may think
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<paul_boddie>
No progress on the jz4740 interrupt quest. :-/
<larsc>
only one of the cpu irqs is used
<larsc>
#3
<larsc>
everything else is on a second level irq chip
<pcercuei>
#2
<pcercuei>
I think
<paul_boddie>
What puzzles me is the actual bare-metal initialisation. Everyone seems to set BEV to 1, but the PM indicates that a bunch of 0xbfc0.... addresses would be used then.
<paul_boddie>
The cleanest code I've seen is actually in Rockbox. Linux is a bunch of #ifdefs.
<paul_boddie>
I'm probably making lots of beginner mistakes, especially with GNU as and MIPS, although I'm figuring them out as I go along.
<paul_boddie>
It's all rather frustrating, as I actually have booting working over USB and from SD, with the framebuffer functional.
<paul_boddie>
The timer is working, I'm unmasking the timer IRQ, leaving only the actual IRQ dispatch a mystery.
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<DocScrutinizer05>
timer most likely does no IRQ servicing (reset IRQ cause in peripheral), is probably edge triggered, and thus simpler than "normal" IRQs
<paul_boddie>
Yes, the timer stuff can be read straight out of a register. But actual interrupt stuff is desirable for more advanced purposes.
<DocScrutinizer05>
sure, it's just more involved
<paul_boddie>
It's difficult to know if things are actually doing something sensible without serious debugging gear, though.
<paul_boddie>
Like whether the CPU is just ignoring the bit combination I set on its register because I didn't set something else first.
<DocScrutinizer05>
IRQ (auto-locks) -> jump to IRQ handler which does: {fetch data from peripheral; reset peripheral IRQ-enable (when not done implicitly by reading data); hand over data to an IRQ deferred handler (often called worker thread) and schedule that worker thread for eventual execution; atomic local IRQ enable and return-from-IRQ}
<DocScrutinizer05>
to debug that stuff you basically only can write a byte to a meaningful location at checkpoints. Ideally a GPIO that makes an LED shine up
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<paul_boddie>
All that the handler really needs to do is to change a single memory location and I'd see it working.
<DocScrutinizer05>
yes
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<paul_boddie>
Which makes me think that whatever I set the damned register to, it either changes the memory map (obvious hang) or does nothing (and my program runs uninterrupted).
<larsc>
low level bootstrapping is always the hardest
<paul_boddie>
I wish someone had written a recipe for this stuff. That would be worth having for just about every new device.
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<DocScrutinizer05>
start with a IRQ handler consisting of max 20 assembler instructions, to blink a LED in an endless loop
<DocScrutinizer05>
oh, and I shouldn't say that, but: test the LED blinker code first, by jumping directly to "start". Only then use it as IRQ handler in next iteration
<larsc>
the beeper
<DocScrutinizer05>
what's NN ops/s?
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<DocScrutinizer05>
ballpark
<DocScrutinizer05>
after reset
<paul_boddie>
Well, it's 336 MHz, but that's just the CPU.
<DocScrutinizer05>
good enough
<DocScrutinizer05>
prolly in the range 10 to 100 ops/s then
<DocScrutinizer05>
Mops/s
<DocScrutinizer05>
;-P
<DocScrutinizer05>
Mips
<paul_boddie>
335.05 BogoMIPS according to the Qi-Hardware site.
<DocScrutinizer05>
then for beeper a single 16bit register for a single DJNZ is sufficient to get sth audible
<DocScrutinizer05>
for a 0.1s beep each time you call the IRQ handler
<DocScrutinizer05>
where RETI maybe doesn't exist on this ISA and needs to get implemented in the correct way by re-enabling the IRQ and atomically returning from subroutine
<DocScrutinizer05>
often the enable-irq command has a one instruction delay until it takes effect, so the return-from-sub instruction gets always executed even when a new IRQ is already pending
<paul_boddie>
It's ERET on MIPS, as far as I can tell.
<DocScrutinizer05>
good, then it has atomic return from subroutine with IRQ enable :-)
<paul_boddie>
Well, to start my sanity checking, I got the screen to show the bit patterns from memory locations where the handlers should be.
<paul_boddie>
They seem to match up with the instructions from my disassembled program.
<paul_boddie>
Think of it being a bit like the Pioneer probe's artwork but without the naked people. :-)
<pcercuei>
< DocScrutinizer05> good, then it has atomic return from subroutine with IRQ enable :-)
<pcercuei>
nope
<DocScrutinizer05>
hmm
<paul_boddie>
I was worried about caching, but it seems like what I put in 0x8000.... is actually what the CPU can read.
* paul_boddie
almost misses writing ARM assembly language from back in the day.
<DocScrutinizer05>
so what's the method of choice for leaving IRQ handler on this ISA?
<pcercuei>
I'd have to verify this, but I'm pretty sure that ERET doesn't change the program counter
<DocScrutinizer05>
so what does it do?
<DocScrutinizer05>
Enable @ next RETurn?
<DocScrutinizer05>
those RISC assembler codes sometimes drive me nuts
<pcercuei>
sorry, got confused with the RFE opcode
<pcercuei>
(Return From Exception)
<DocScrutinizer05>
hmm, sounds almost similar
<pcercuei>
RFE is a CP0 opcode on mips1
<DocScrutinizer05>
just it changes the status bits
<DocScrutinizer05>
but also should change PC
<paul_boddie>
It's all a nasty mess of real opcodes, pseudo-opcodes and several generations of cruft.
<DocScrutinizer05>
yeah
<paul_boddie>
On the imgtec blog a while back there were some catty remarks about "other RISC architectures", which I interpreted as being aimed at ARM.
<DocScrutinizer05>
ARM is a mess too
<pcercuei>
I think mips v6 cleans that up
<pcercuei>
mips32r6
<paul_boddie>
Modern ARM probably is. The instruction format is awkward, so I'm told.
<paul_boddie>
"you could pick ARM, but that's also become increasingly complex, and was arguably never true RISC in the first place"
<paul_boddie>
The only non-RISC thing I can think of with the original ARM are the multiple load/store instructions, which are actually a good idea.
<paul_boddie>
(I guess some people here or on #m-labs would have something to say about that article, anyway.)
<DocScrutinizer05>
what happened to all the really good CPU technical manuals) like e.g. the original Zilog Z80 manual
<DocScrutinizer05>
?
<paul_boddie>
I know. I also dabble in retro stuff and some of those early manuals are quite good.
<paul_boddie>
Even the outsiders like MOS and their licencees put out reasonable manuals. Nothing like the stuff I see here with missing chapters and "don't ask me I only work here" explanations.
<DocScrutinizer05>
yeah, they *really* explained such stuff like IRQ (handlers) - with example code and all
<paul_boddie>
Example code? These days people have forgotten that the CPU actually does something so dirty as to run code!
<DocScrutinizer05>
indeed
<paul_boddie>
I think that there's a technical gap in most companies now where the doc writers don't actually know anything else.
<paul_boddie>
I sometimes wonder whether some of the engineers actually understand their area, either.
<paul_boddie>
OK, on to a more practical test: incrementing a counter and trying to show that.
<DocScrutinizer05>
that's what your timer IRQ already does ;-)
<paul_boddie>
If only!
<larsc>
fake it until you make it!
<paul_boddie>
Still faking it, I'm afraid.
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<paul_boddie>
Stupid question: can the jz4740 actually be interrupted in kernel mode?
<paul_boddie>
All the docs talk about combinations of KSU (or UM) and ERL and EXL, and some mention interrupts being enabled or disabled for some combinations.
<paul_boddie>
The R4000 manual mentions this.
<larsc>
sure
<paul_boddie>
"Interrupt Enable: Interrupts are enabled when all of the following conditions are true: IE = 1; EXL = 0; ERL = 0"
<paul_boddie>
If I clear ERL, which is set at reset time, the device hangs. I imagine that clearing ERL causes some mode transition.
<pcercuei>
or youa get an interrupt maybe
<pcercuei>
you*
<DocScrutinizer05>
exactly :-)
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<paul_boddie>
I did think that, together with my handlers not working, of course.
<DocScrutinizer05>
that's the "usual" scenario ;D
<DocScrutinizer05>
that's why you want a "LED blinker" IRQ handler routine, to start with
<DocScrutinizer05>
even better: a beeper-yell IRQ handler like sketched above
<DocScrutinizer05>
which would allow the device to continue "normal" operation even when IRQ handler gets invoked
<paul_boddie>
But what is strange is that as soon as I clear ERL, even if the interrupt enable flag is clear, I get the hang.
<paul_boddie>
Which suggests that some other mechanism is involved. The initial reset condition is like an exception condition, which is why I wondered about special magic when you clear the ERL bit.