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<DocScrutinizer05>
re >>the configuration bitstream is 100% documented in the device datasheet! << Andrew admitted it was only the bit order and meaning in the NVM/matrix, the _protocol_ however is not documented at all
<DocScrutinizer05>
at least not publicly, seems he received internal docs from silego about some of the protocol details
<DocScrutinizer05>
unlike us ;-)
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<wpwrak>
DocScrutinizer05: (where) it's the register bits that are mentioned all over the data sheet
<DocScrutinizer05>
see ^^^
<wpwrak>
ah yes, catching up
<DocScrutinizer05>
you noticed the /invite andrew sent to you?
<wpwrak>
yup. in the article he called it the SRAM documentation
<wpwrak>
but in any case, with the GP5 we could even do without that (to a certain point)
<DocScrutinizer05>
yep
<DocScrutinizer05>
(invite) ##openfpga
<DocScrutinizer05>
you'll notice 3 well known users already
<DocScrutinizer05>
;-)
<wpwrak>
yes yes, in the post i saw whitequark mentioned. and we know azonenberg well from qi-hw and milkymist :)
<DocScrutinizer05>
aaah
<DocScrutinizer05>
didn't know
<DocScrutinizer05>
azonenberg and whitequark in one place, what could be impossible to happen with this constellation ;-)
<wpwrak>
indeed :)
<DocScrutinizer05>
[2016-06-30 Thu 09:40:54] <azonenberg> https://siliconpr0n.org/wiki/doku.php?id=physical_protection [2016-06-30 Thu 09:41:30] <DocScrutinizer05> did they mention C4 or other explosives? [2016-06-30 Thu 09:41:56] <azonenberg> DocScrutinizer05: ^f LOPPER
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