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<Venemo_j> hey
<Venemo_j> just out of curiosity, how do you guys do power supply in the Neo900?
<Venemo_j> is it a buck-boost converter, or just an LDO?
<DocScrutinizer05> buck boost
<DocScrutinizer05> ~bd
<Venemo_j> uh, is it in the “companion”?
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<Venemo_j> the TPS65950?
<DocScrutinizer05> there are a 2 dozen power regulators in the Neo900
<DocScrutinizer05> many in the TWL4030 aka TPS65950
<DocScrutinizer05> when you said "power supply" I thought charging
<DocScrutinizer05> which is a bq24xxx
<Venemo_j> mhm
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<Venemo_j> why do you need so many?
<DocScrutinizer05> because there are a dozen different power domains from 1.2V(?) up to 5V
<DocScrutinizer05> unrelated: Order Date :JUL 31, 2014 Mouser Part Number 595-BEAGLEBOARD-XM Estimated Shipment Date(s) JUL 11, 2016
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<DocScrutinizer05> ceene: hi! we need to get to pace with the layouting job
<DocScrutinizer05> ceene: I'm back in ~ 2h
<DocScrutinizer05> maybe we can continue then?
<ceene> uhmmmmm don't know where i'll be in two hours from now
<ceene> but ping me in any case
<DocScrutinizer05> I'll do
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<wpwrak> ceene, ahycka: i think the basic questions are a) whether you've had time to have a good look at the current v2 schematics yet, and, based on that, b) have a rough idea of how much work the layout would be (in terms of time and money)
<DocScrutinizer05> and 0) if you got time and intention to do the job
<wpwrak> ceene, ahycka: this should be the PDF that's easiest to navigate: https://neo900.org/stuff/werner/tmp/Neo900-toc.pdf (has a PDF TOC). but maybe joerg already sent you the latest Eagle design files.
<wpwrak> DocScrutinizer05: we have to be optimistic ;-)
<DocScrutinizer05> apropos TOC, all schematics are supposed to have one now, no?
<DocScrutinizer05> I wrote that nifty Eagle ULP for a purpose ;-)
<DocScrutinizer05> grr
<wpwrak> ;-)
<wpwrak> i'm actually not entirely sure if your ULP does the same thing. in any case, my critter is here: https://neo900.org/git/?p=misc;a=tree;f=schtoc
<wpwrak> the Makefile shuold be self-explaining. schtoc.pl, well, so-so ;-)
<DocScrutinizer05> huh? sure my ULP does the same thing, you even used it in scripting mode
<wpwrak> i just run "print 20 -1 file ./$tmp landscape sheets all; quit;", then i work on the PDF
<wpwrak> well, and i also parse the .sch
<DocScrutinizer05> the problem with this approach is: it's not backward compatible to Eagle
<DocScrutinizer05> so printing sheets from Eagle wouldn't have a TOC
<wpwrak> but i think your ULP does something different: it generates a page with sheet title and page numbers, no ? but not a PDF toc (the thing you can use to navigate)
<wpwrak> sure, schtoc.pl is a post-processor
<DocScrutinizer05> aah, right
<DocScrutinizer05> eagle got NFC about pdf index
<DocScrutinizer05> I thought your schtoc.pl creates the TOC sheet
<wpwrak> yeah. those TOC are also fairly tricky. you have to create a tree of toc entry objects. and if you want to put it into an existing pdf, yuo need to patch some pointers
<wpwrak> was an interesting learning experience, though :)
<DocScrutinizer05> so bot the ULP and yours are complementary
<DocScrutinizer05> both
<ceene> wpwrak, DocScrutinizer05: we haven't looked at it all thoroughly, so we can't answer (b) yet
<ceene> ahycka is willing to do it, but doesn't want to be paid nor can promise any time, as that'll be done on her free time
<ceene> as payment she accepts a prototype, or something like that, so she at least has one copy of what she's built
<ceene> we have access to quite a decent lab, so we'd be able to test lots of things
<DocScrutinizer05> that sounds good, we just need some fairly binding timelines we try to keep
<ceene> we'll print the schematics tomorrow and make a valoration of how much time it can take
<ceene> valoration is an english word?
<ceene> evaluation
<DocScrutinizer05> hehe, spanish
<wpwrak> DocScrutinizer05: have you sent them the design files yet ? especially footprints (to the extent that they're present) may be a significant time factor
<DocScrutinizer05> I wasn't even sure
<DocScrutinizer05> yes
<ceene> the files we got are latest versions?
<DocScrutinizer05> the footprints are embedded as far as we got them at all from Nikolaus
<DocScrutinizer05> yes
<ceene> if she does it in altium she'll be faster, that's for sure
<DocScrutinizer05> we need to discuss this
<ceene> i'm not good routing, but i can for sure draw missing footprints
<DocScrutinizer05> for the prototype we won't have a need to ever access the layout of at least UPPER in Eagle again
<DocScrutinizer05> it's a one-off
<ceene> so, for this prototype
<DocScrutinizer05> for the final layout the situation is a tad different
<wpwrak> but any footprint should be reusable from v2 to v3 / final
<DocScrutinizer05> a) we need sophisticated FPBGA routing there, and b) we need a sustainable toolchain to handle it
<ceene> thing is we've only ever used altium, i used something from national instruments years ago, don't remember its name
<ceene> but kicad and eagle are new for us
<DocScrutinizer05> Eagle is crap for the complexity of layout we need for final, anyway
<ceene> so maybe we should just discard it forever
<DocScrutinizer05> Nikoluas dealt with this by using his own proprietary rouer
<wpwrak> and i'm (still :-( ) not sure if kicad could do it. i have done 2 layer with the manual router, but still have to try the push router for a "real" design
<ceene> we've exported one of our own designs in altium to kicad and it looked very good
<DocScrutinizer05> what woukd be *really* great was a viable export feature from Altium into a format that actually works for Eagle and maybe even kicad
<ceene> so at least, if we route on altium i think it's safe to say kicad compatibility will be near 100%
<wpwrak> ceene: could you follow traces across layers ? i.e., was the converted version able to have proper netlists in the layout editor ?
<DocScrutinizer05> that sounds great
<ceene> altium2kicad works great i think
<ceene> wpwrak: i think so, yeah, it highlited connected pads, traces and all that
<DocScrutinizer05> ((Eagle)) can't even do in-pad vias >:-((
<wpwrak> ceene: okay, that sounds very encouraging
<wpwrak> DocScrutinizer05: time to shoot the lame bird :)
<ceene> we can't release this pcb, as its of our company, but we can try some example pcb from altium and export it to kicad, so yu can evaluate if it would fit
<DocScrutinizer05> only manually, with lots of asskicking
<ceene> well, gonna have dinner now, tomorrow we'll look at the schematics
<ceene> both boards need to be done for this prototype?
<DocScrutinizer05> ((kicad)) could the two (three?) of you take care of that?
<ceene> we've never used kicad, but it seems usable
<DocScrutinizer05> ceene: have a carachilo on me ;-)
<DocScrutinizer05> yes, both boards UPPER and LOWER needed for proto_v2
<ceene> that translates basically on more time till we learn how to use kicad
<wpwrak> that must be deep spanish slang :)
<ceene> well, that's a carajillo :)
<ceene> ch in german is similar to the j
<DocScrutinizer05> salut, pesetas, y muceres is spanish 'slang'
<DocScrutinizer05> mucheres*
<DocScrutinizer05> mijeres?
<ceene> mujeres
<DocScrutinizer05> dang, my typing sucks
<ceene> carajillo is coffee with cognac/brandy
<ceene> also, salud :)
<DocScrutinizer05> delicious
<ceene> salud, mujeres y amor
<DocScrutinizer05> :-D
<ceene> it's like the healthy version of sex, drugs and rock&roll
<DocScrutinizer05> hehe
<ceene> well, cya tomorrow, we'll tell you something tomorrow
<DocScrutinizer05> don't forget the chip of orange peel in the carajillo
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