<omnitechnomancer> etrig: cool I will try to actually end up using mine
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<omnitechnomancer> Is there a good reason to use newer xilinx tools for zynq? I currently have a 2017 version whichever one x-ray requires
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<daveshah> omnitechnomancer: ime, newer Vivados are a bit faster
<omnitechnomancer> are they also larger when installed?
<daveshah> x-ray only needs 2017 to run one specific fuzzer aiui, I have done various x-ray things with 2019 and 2020
<daveshah> Never actually needed 2017
<omnitechnomancer> I see
<omnitechnomancer> Are the newer Vivado's larger though, I care about my precious disk space :P
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<lambda> omnitechnomancer: yeah, they get significantly and inexplicably larger every year
<omnitechnomancer> alas
<implr> 19G /opt/Xilinx/14.7/ISE_DS
<implr> 7.1G /opt/Xilinx/Vivado/2016.2
<implr> 21G /opt/Xilinx/Vivado/2019.1
<implr> 52G /opt/Xilinx/Vivado/2020.1
<implr> 26G /opt/Xilinx/Vitis/2020.1
<implr> 2020 is quite chonky
<implr> although i think my 2016 install is incomplete
<omnitechnomancer> What is Vitis?
<implr> good question, i'm not sure myself
<implr> part of their unified software thing, replaced the old sdk
<omnitechnomancer> Hmm 2019 may be about the same size as I have already but 2020 is way too big
<implr> but on a surface level it is still an eclipse
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<omnitechnomancer> Ah okay
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<omnitechnomancer> 26GB of eclipse and sundry
<implr> seems it includes: four qemus, four gccs, two clangs
<implr> and then a ton of per-part blobs
<sorear> how many nodes and jvms?
<implr> including a mysterious data/cache/xilinx with 9G total of vhdl and verilog files, ~40M each
<implr> sorear: seems like just one, for the eclipse
<implr> a decent part of the chonk is just their .so libs, guessing it's the magical HLS compiler
<rvense> are they at least qemus and gccs for different architectures?
<implr> hum it seems there are actually *more* gccs
<implr> duplicated x86 ones
<implr> the previously mentioned four are arm aarch64 microblaze armr5, so reasonable
<sorear> armr5?
<daveshah> Cortex-R5?
<daveshah> Thats what the Zynq Ultrascales use for their realtime cores
<sorear> I'm wondering what the difference between that and the
<sorear> 'arm' gcc is
<sorear> I thought you could use a single gcc to target all aarch32
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<omnitechnomancer> I suppose it being gcc they have to build two if they want a freestanding one, though isn't all of that freestanding?
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<omnitechnomancer> What is the difference between the general purpose and high performance AXI Slave interfaces on the Zynq 7?
<keesj> I like using the command line ncdu tool to scroll though the file system and find the biggest offenders (my 2019.1 is 24 G) but there is also an additional 8G in the SDK directory
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<implr> omnitechnomancer: HP is 64bit wide and connects more directly to the ddr controller
<implr> while GP is 32bit and hangs off the main crossbar with every other peripherial
<implr> iirc no meaningful differences in using them except hp is just much faster
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<zyp> can you use the HP one to access other stuff than the DDR controller?
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<omnitechnomancer> zyp: I don't think so, except maybe some on chip ram
<vup> omnitechnomancer: HP also has QoS settings I think, which can be useful to prioritize the HP traffic vs the traffic coming from the arm cores
<zyp> I mean, that would also be a significant difference then
<omnitechnomancer> Indeed
<implr> zyp: ah, duh, of course
<implr> haven't done any PL->fixed peripherial dma, forgot it was a thing
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<omnitechnomancer> I only want to use the DDR memory anyway so that difference is not very important to me right now
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